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公开(公告)号：US07774528B2
公开(公告)日：2010-08-10
申请号：US11913064
申请日：2006-05-01
CPC分类号： G06F13/4291 , G06F2213/0016
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master.
摘要翻译： 与一个示例性实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统使用设备识别编码并入集成电路从设备的标识。 通信系统包括具有识别一个或多个参数的设备标识码的从设备。 从设备中的通信电路配置为使用通信协议与I2C串行数据传输总线上的主设备进行通信。 响应于从主设备发送设备标识地址，从设备被配置为发送ACKNOWLEDGE，并且响应于从主设备发送从设备地址和设备标识地址，从设备是 被配置为将设备标识码从从设备发送到主设备。
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公开(公告)号：US20080147941A1
公开(公告)日：2008-06-19
申请号：US11913069
申请日：2006-05-01
IPC分类号： G06F13/18
CPC分类号： G06F13/4068 , G06F13/4291
摘要： Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.
摘要翻译： 与一个示例实施例一致，通信系统使用具有用于实现通信协议的串行数据线（110）和时钟线（120）的I2C串行数据传输总线。 通信系统包括具有地址引脚（400）的从设备，每个耦合到串行数据线，时钟线，电源线或接地。 通信电路根据通过数据传输总线的通信协议与主设备进行通信。 解码电路检测地址引脚（410）的第一状态，在检测到第一状态之后检测地址引脚（420）的第二状态，其中地址引脚的一个或多个逻辑值在第一状态和 第二状态，并且将从设备地址（430）解码为地址引脚的第一状态和第二状态之间的功能关系。
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公开(公告)号：US06522169B2
公开(公告)日：2003-02-18
申请号：US10027672
申请日：2001-12-19
申请人： Alma Anderson , Paul Andrews
发明人： Alma Anderson , Paul Andrews
IPC分类号： H03K190175
CPC分类号： G06F13/4045 , G06F2213/0016
摘要： A repeater employs multiple threshold detectors to distinguish between signals from external devices and signals generated within the repeater. Signals that are sent from the repeater are configured to be between two threshold levels, so that a detector at one threshold level will detect an active signal, but the detector at the other threshold level will not detect an active signal. When an external signal is received on one side (A) of the repeater, it is propagated to the other side (B) of the repeater, and at the same time, the other side (B) of the repeater is configured to only propagate external signals back to the first side (A). In this manner, the internally generated signal from one side (A) is not propagated back to the same side (A), and a latch-up is avoided. In like manner, when an external signal is received at the other side (B), the first side (A) of the repeater is configured to propagate only externally generated signals. If both sides of the repeater are externally driven, the active signal is propagated to both sides of the repeater, thereby emulating the response that would be provided by a wired bus without a repeater. The repeater is particularly well suited for an I2C bus architecture.
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公开(公告)号：US06433622B1
公开(公告)日：2002-08-13
申请号：US09642181
申请日：2000-08-17
申请人： Alma Anderson , Howard Paul Andrews
发明人： Alma Anderson , Howard Paul Andrews
IPC分类号： G05F110
CPC分类号： H03K17/166
摘要： The invention provides a voltage stabilized low level driver. The driver includes a switched op-amp that controls the output of the driver to match an internal reference voltage when it is switched on. When it is switched off, the op-amp turns off the output of the driver and allows the output to be pulled up by an external device. The driver also includes a slew rate control circuit for limiting the slew rate of the high-to-low transition at the output. The driver may be used for I2C applications.
摘要翻译： 本发明提供一种电压稳定的低电平驱动器。 该驱动器包括一个开关运算放大器，用于控制驱动器的输出，以便在接通时匹配内部参考电压。 当关闭时，运算放大器关闭驱动器的输出，并允许输出由外部设备上拉。 驱动器还包括一个压摆率控制电路，用于限制输出端的高电平到低电平转换的转换速率。 该驱动器可用于I2C应用。
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15.发明授权Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid 失效可编程逻辑集成电路包括验证电路，用于将熔丝状态分类为有效关闭，有效打开或无效
公开(公告)号：US5635854A
公开(公告)日：1997-06-03
申请号：US247934
申请日：1994-05-24
摘要： A programmable logic device (PLD) integrated circuit containing an array of fuse or anti-fuse links includes verification circuitry configured to classify link resistances after programing into three resistance zones, corresponding to a "closed" state zone, an "open" state zone and a "forbidden" state zone intermediate the "closed" and "open" state zones. Two reference resistance values, namely a lower reference resistance value and the higher reference resistance value, divide the entire range of possible link resistance values into the aforementioned three resistance zones. Because the ratio between the higher reference resistance value and the lower reference resistance value is typically more than 50, the verification circuitry includes a switchable two level current source that produces a voltage across the link of correct dynamic range. A measurement voltage produced in response to the link voltage is compared by a pair of differential comparators to respective lower and higher reference voltages, the lower reference voltage corresponding to the measurement voltage that would be produced by a higher link voltage that is the product of the higher reference resistance value and the lower current level, and the higher reference voltage corresponding to the measurement voltage that would be produced by a lower link voltage that is the product of the lower reference resistance value and the higher current level.
摘要翻译： 包含熔丝或反熔丝链路阵列的可编程逻辑器件（PLD）集成电路包括验证电路，其被配置为将编程之后的链路电阻分类为三个电阻区域，对应于“闭合”状态区域，“开放”状态区域和 “封闭”和“开放”状态区之间的“禁止”状态区。 两个参考电阻值，即较低的参考电阻值和较高的参考电阻值，将可能的链路电阻值的整个范围划分为上述三个电阻区域。 因为较高的参考电阻值和较低的参考电阻值之间的比率通常大于50，所以验证电路包括一个可切换的两电平电流源，它产生跨越链路的正确动态范围的电压。 将响应于链路电压产生的测量电压通过一对差分比较器与相应的较低和较高参考电压进行比较，较低的参考电压对应于由较高链路电压产生的测量电压，该较高链路电压是 较高的参考电阻值和较低的电流电平，以及较高的参考电压对应于由较低的参考电阻值和较高电流电平的乘积产生的较低链路电压产生的测量电压。
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公开(公告)号：US07788431B2
公开(公告)日：2010-08-31
申请号：US11913069
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F13/4068 , G06F13/4291
摘要： Consistent with one example embodiment, a communications system uses an I2C serial data transfer bus that has a serial data line (110) and a clock line (120) used to implement a communications protocol. The communications system includes a slave device having address pins (400), each coupled to the serial data line, clock line, power line, or ground. Communications circuitry communicates with a master device in accordance with the communications protocol over the data transfer bus. Decoding circuitry detects a first state of the address pins (410), detects a second state of the address pins (420) subsequent to the detection of the first state, wherein one or more logic values of the address pins differ between the first state and the second state, and decodes a slave device address (430) as a functional relationship between the first state and the second state of the address pins.
摘要翻译： 与一个示例实施例一致，通信系统使用具有用于实现通信协议的串行数据线（110）和时钟线（120）的I2C串行数据传输总线。 通信系统包括具有地址引脚（400）的从设备，每个耦合到串行数据线，时钟线，电源线或接地。 通信电路根据通过数据传输总线的通信协议与主设备进行通信。 解码电路检测地址引脚（410）的第一状态，在检测到第一状态之后检测地址引脚（420）的第二状态，其中地址引脚的一个或多个逻辑值在第一状态和 第二状态，并且将从设备地址（430）解码为地址引脚的第一状态和第二状态之间的功能关系。
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17.发明授权公开(公告)号：US07711867B2
公开(公告)日：2010-05-04
申请号：US11913065
申请日：2006-05-01
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I2C serial bus. At least two slave devices are coupled in parallel on the data transfer bus and configured to load serial data over the serial data line using the communications protocol. Each slave device includes a programmable configuration register configured to be programmed, using the communications protocol, to select one of a plurality of selectable slave device configurations. One of the selectable slave device configurations causes the at least two slave devices to load the serial data in parallel, and another of the selectable slave device configurations causes the at least two slave devices to be loaded one at a time.
摘要翻译： 与一个示例性实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统使用I2C串行总线并行编程并行从设备。 至少两个从设备在数据传输总线上并联耦合，并配置为使用通信协议通过串行数据线加载串行数据。 每个从设备包括可编程配置寄存器，其被配置为使用通信协议来编程以选择多个可选择的从设备配置中的一个。 可选择的从设备配置之一使得至少两个从设备并行加载串行数据，另一个可选择的从设备配置使得至少两个从设备一次一个地加载。
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公开(公告)号：US20080215780A1
公开(公告)日：2008-09-04
申请号：US11913063
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统将逻辑值的可编程加载并入到并行从设备寄存器中。 通信系统包括具有两个或更多个寄存器的从设备，每个寄存器具有两个或多个位，每个寄存器被配置为在第一配置中通过数据传输总线加载根据通信协议接收的数据，并且加载单个 第二配置中的多个位的逻辑值。 可编程配置寄存器被配置为根据数据传输总线上的通信协议来编程，以选择两个或更多个用于将单个逻辑值加载到所选择的寄存器的两个或更多个位中的寄存器 第二配置。
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公开(公告)号：US20080201511A1
公开(公告)日：2008-08-21
申请号：US11913064
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F2213/0016
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master.
摘要翻译： 与一个示例性实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统使用设备识别编码并入集成电路从设备的标识。 通信系统包括具有识别一个或多个参数的设备标识码的从设备。 从设备中的通信电路配置为使用通信协议与I2C串行数据传输总线上的主设备进行通信。 响应于从主设备发送设备标识地址，从设备被配置为发送ACKNOWLEDGE，并且响应于从主设备发送从设备地址和设备标识地址，从设备是 被配置为将设备标识码从从设备发送到主设备。
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公开(公告)号：US20080189458A1
公开(公告)日：2008-08-07
申请号：US11913057
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable updating of slave device output banks sequentially or simultaneously. The communications system includes two or more slave devices and/or a slave device having two or more banks of output drivers. Each slave device receives serial data and provides a data word assembled from the serial data. A programmable register in each slave device is programmed, using the communications protocol, to select one or more slave device configurations. Each of the two or more slave devices and/or two or more banks of output drivers updates either sequentially, or in coordination with other of the two or more slave devices and/or two or more banks of output drivers, based on each slave devices configuration selected by its programmable register.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统并入或并行地并入从属设备输出组的可编程更新。 通信系统包括两个或更多个从设备和/或具有两个或更多个输出驱动器组的从设备。 每个从设备接收串行数据并提供从串行数据组装的数据字。 使用通信协议对每个从设备中的可编程寄存器进行编程，以选择一个或多个从设备配置。 基于每个从设备，两个或更多个从设备和/或两个或更多个输出驱动器组中的每一个依次或与两个或更多个从设备中的其他设备和/或两个或更多个输出驱动器组配合地更新 配置由其可编程寄存器选择。
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