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公开(公告)号:US11055252B1
公开(公告)日:2021-07-06
申请号:US15012409
申请日:2016-02-01
Applicant: Amazon Technologies, Inc.
Inventor: Kypros Constantinides , Darin Lee Frink
Abstract: A system includes a rack with multiple hardware acceleration devices and at least one modular controller coupled together into one or more particular processing systems. Each modular hardware acceleration device includes multiple hardware accelerators, such as graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other specialized processing circuits. In each modular hardware acceleration device, the multiple hardware accelerators are communicatively coupled to a multi-port connection device, such as a switch, that is also communicatively coupled to at least two external ports of the modular hardware acceleration device. A modular controller of a particular processing system coordinates operation of hardware accelerators of multiple hardware acceleration devices included in the particular processing system to provide advanced processing capabilities. Modular hardware acceleration devices may be added to or taken away from particular processing systems to adjust advanced processing capabilities of the particular processing systems.
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公开(公告)号:US11003618B1
公开(公告)日:2021-05-11
申请号:US15635038
申请日:2017-06-27
Applicant: Amazon Technologies, Inc.
Inventor: Kypros Constantinides , Nafea Bshara , Matthew Shawn Wilson
Abstract: Disclosed are techniques regarding aspects of selectively enabling or disabling interconnects between peripheral processors. The peripheral processors may be included within a compute service provider and may be accessible via virtual machines within guest domains implemented within the compute service provider. The interconnects can be enabled or disabled depending upon whether they traverse domains of the compute service provider.
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公开(公告)号:US20190258597A1
公开(公告)日:2019-08-22
申请号:US16287986
申请日:2019-02-27
Applicant: Amazon Technologies, Inc.
Inventor: Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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公开(公告)号:US20210182230A1
公开(公告)日:2021-06-17
申请号:US17184507
申请日:2021-02-24
Applicant: Amazon Technologies, Inc.
Inventor: Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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公开(公告)号:US10963414B2
公开(公告)日:2021-03-30
申请号:US16287986
申请日:2019-02-27
Applicant: Amazon Technologies, Inc.
Inventor: Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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公开(公告)号:US20180089132A1
公开(公告)日:2018-03-29
申请号:US15279232
申请日:2016-09-28
Applicant: Amazon Technologies, Inc.
Inventor: Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
CPC classification number: G06F13/4068 , G06F9/44505 , G06F13/4282 , G06F15/7867 , G06F15/7871
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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