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    Networked programmable logic service provider
    1.
    发明授权
    Networked programmable logic service provider 有权

    公开(公告)号：US11863406B2

    公开(公告)日：2024-01-02

    申请号：US17466944

    申请日：2021-09-03

    Applicant: Amazon Technologies, Inc.

    Inventor： Robert Michael Johnson ,  Nafea Bshara ,  Matthew Shawn Wilson

    IPC: H04L12/24 ,  G06F9/50 ,  G06F15/78 ,  H04L41/5054 ,  H04L41/50

    CPC classification number: H04L41/5054 ,  G06F9/50 ,  G06F15/7871 ,  H04L41/5096

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

    Broadcasting writes to multiple modules
    3.
    发明授权
    Broadcasting writes to multiple modules 有权

    公开(公告)号：US10649923B1

    公开(公告)日：2020-05-12

    申请号：US16250995

    申请日：2019-01-17

    Applicant: Amazon Technologies, Inc.

    Inventor： Asif Khan ,  Robert Michael Johnson

    IPC: G06F13/16 ,  G06F13/40

    Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

    Configurable logic platform
    5.
    发明授权
    Configurable logic platform 有权

    公开(公告)号：US10223317B2

    公开(公告)日：2019-03-05

    申请号：US15279232

    申请日：2016-09-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Broadcasting reads to multiple modules
    6.
    发明授权
    Broadcasting reads to multiple modules 有权

    公开(公告)号：US10180919B1

    公开(公告)日：2019-01-15

    申请号：US14983154

    申请日：2015-12-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Robert Michael Johnson ,  Asif Khan

    IPC: G06F13/16 ,  G06F13/40

    Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

    NETWORKED PROGRAMMABLE LOGIC SERVICE PROVIDER
    7.
    发明申请
    NETWORKED PROGRAMMABLE LOGIC SERVICE PROVIDER 审中-公开

    公开(公告)号：US20180139110A1

    公开(公告)日：2018-05-17

    申请号：US15354765

    申请日：2016-11-17

    Applicant: Amazon Technologies, Inc.

    Inventor： Robert Michael Johnson ,  Nafea Bshara ,  Matthew Shawn Wilson

    IPC: H04L12/24

    CPC classification number: H04L41/5054 ,  G06F9/50 ,  G06F15/7871 ,  H04L41/5096

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

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