CONFIGURABLE LOGIC PLATFORM
    4.
    发明申请

    公开(公告)号:US20210182230A1

    公开(公告)日:2021-06-17

    申请号:US17184507

    申请日:2021-02-24

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Configurable logic platform
    5.
    发明授权

    公开(公告)号:US10963414B2

    公开(公告)日:2021-03-30

    申请号:US16287986

    申请日:2019-02-27

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Reconfiguring programmable hardware when a virtual machine is active

    公开(公告)号:US10776142B1

    公开(公告)日:2020-09-15

    申请号:US15840807

    申请日:2017-12-13

    Abstract: Disclosed herein are techniques for configuring a shell logic in a configurable computing system while a client virtual machine (VM) using the shell logic is active. In certain embodiments, a configurable device includes a client configurable circuit associated with a client virtual machine, and a shell logic configured to isolate the client configurable circuit. The shell logic includes a reconfigurable shell, an isolation logic, and a packet processing logic. The isolation logic is configured to disable communication between the reconfigurable shell and the client virtual machine when the reconfigurable shell is being reconfigured. The packet processing logic is configured to service transactions between the client virtual machine and the configurable device after the communication between the reconfigurable shell and the client virtual machine is disabled. In some embodiments, the shell logic also includes a mailbox configured to enable communication between the client virtual machine and a management virtual machine.

    Broadcasting reads to multiple modules

    公开(公告)号:US10649928B1

    公开(公告)日:2020-05-12

    申请号:US16247339

    申请日:2019-01-14

    Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

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