公开(公告)号：US06784752B2

公开(公告)日：2004-08-31

申请号：US10131288

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03B500

CPC分类号： G06F1/10 ,  H03L7/081 ,  H03L7/18

摘要： A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

摘要翻译： 提供了一种锁相环，其包括可调整以基本上匹配系统时钟的延迟的接收器和在锁相环的输入处的反馈时钟。 接收机采用系统时钟路径电路来输入系统时钟和反馈时钟路径电路以输入反馈时钟，其中与系统时钟路径电路相关联的电流和负载电阻以及与反馈时钟路径电路相关联的电流和负载电阻是 响应于使用可操作地连接到接收器的一个或多个调节电路可调整的一个或多个偏置信号。 通过一个或多个调整电路对一个或多个偏置信号的控制有助于产生基本上延迟匹配的系统和反馈时钟。

公开(公告)号：US06687881B2

公开(公告)日：2004-02-03

申请号：US10075782

申请日：2002-02-14

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method for optimizing loop bandwidth in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and the loop bandwidth of the delay looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a delay locked loop is provided.

摘要翻译： 提供了一种用于优化延迟锁定环路中环路带宽的方法。 具有噪声的代表性电源波形被输入到延迟锁定环路的仿真中; 确定抖动的估计; 并且调整延迟看环路的环路带宽，直到抖动下降到低于预选值。 此外，提供了一种用于优化延迟锁定环路中的环路带宽的计算机系统。 此外，提供了其上记录有适于优化延迟锁定环路中的环路带宽的指令的计算机可读介质。

公开(公告)号：US06664831B2

公开(公告)日：2003-12-16

申请号：US10131687

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： H03L706

CPC分类号： H03L7/0898 ,  H03L7/0812 ,  H03L7/0896

摘要： A charge pump design that facilitates post-fabrication control of delay locked loop charge pump current is provided. The charge pump includes an adjustment device responsive to user controlled signals that are varied to achieve a desired amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired DLL performance characteristic after the DLL has been fabricated.

摘要翻译： 提供了一种有助于延迟锁定环电荷泵电流的制造后控制的电荷泵设计。 电荷泵包括响应用户控制的信号的调节装置，其被改变以实现所需量的电荷泵电流。 在延迟锁定环路中对电荷泵电流的这种控制允许设计者在DLL被制造之后实现期望的DLL性能特性。

公开(公告)号：US06664828B2

公开(公告)日：2003-12-16

申请号：US10131306

申请日：2002-04-24

申请人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0898 ,  H03L7/0896 ,  H03L7/18

摘要： A post-silicon technique for adjusting a current of a charge pump in a phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to facilitate an internal biasing of the charge pump. Such control of the charge pump current in a phase locked loop allows a designer to achieve desired PLL performance characteristics after the PLL has been fabricated.

摘要翻译： 提供了一种用于调节锁相环中的电荷泵电流的后硅技术。 该技术涉及使用可操作地连接到电荷泵的调节电路，其中调节电路是可控制的，以便于电荷泵的内部偏置。 锁相环中的电荷泵电流的这种控制允许设计者在PLL被制造之后实现期望的PLL性能特性。

公开(公告)号：US06650157B2

公开(公告)日：2003-11-18

申请号：US10044103

申请日：2002-01-11

申请人： Brian Amick ,  Claude Gauthier ,  Dean Liu

发明人： Brian Amick ,  Claude Gauthier ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0814 ,  H03L7/07

摘要： A delay locked loop that uses a differential push/pull buffer is provided. The differential push/pull buffer of the DLL is used to create a buffered output that closely follows the characteristics of the buffer's input over a range of temperature, power supply noise operating conditions, and process (manufacturing) variations. Further, an integrated circuit that contains a delay locked loop that uses a differential push/pull buffer is provided. Further, a delay locked loop with means for buffering a delayed signal is provided. Further, a method for buffering a delayed clock signal using a differential push/pull buffer is provided.

摘要翻译： 提供了使用差分推/拉缓冲器的延迟锁定环。 DLL的差分推/拉缓冲器用于创建缓冲输出，该缓冲输出在温度范围，电源噪声运行条件和过程（制造）变化等方面与缓冲器输入的特性密切相关。 此外，提供了包含使用差分推/拉缓冲器的延迟锁定环路的集成电路。 此外，提供了一种用于缓冲延迟信号的装置的延迟锁定环。 此外，提供了一种使用差分推/拉缓冲器来缓存延迟时钟信号的方法。

公开(公告)号：US07251305B2

公开(公告)日：2007-07-31

申请号：US10147838

申请日：2002-05-17

申请人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

发明人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

IPC分类号： H03D3/24

CPC分类号： H03L7/0812

摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

摘要翻译： 提供了一种用于延迟锁定环偏置发生器的后制造控制的校准和调整系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。 可以存储和随后读取偏置 - 发生器输出中期望的调节量的代表值来调整延迟锁定环。

公开(公告)号：US07106113B2

公开(公告)日：2006-09-12

申请号：US10147841

申请日：2002-05-17

申请人： Claude R. Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude R. Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G06F1/10 ,  H03L7/0891 ,  H03L7/18

摘要： An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

公开(公告)号：US06639439B2

公开(公告)日：2003-10-28

申请号：US09981385

申请日：2001-10-16

申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

IPC分类号： H03L706

CPC分类号： H03L7/06

摘要： A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’

摘要翻译： 已经开发了一种用于降低锁相环电源系统中的电压变化的方法。 该方法包括上电锁相环，并在电源端子上激活或插入分流电阻。 分流电阻与锁相环平行插入，并且可控制，使得电阻可以选择性地“接通”和/或“关闭”。

公开(公告)号：US06556041B1

公开(公告)日：2003-04-29

申请号：US09978869

申请日：2001-10-16

申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

IPC分类号： H03K1716

CPC分类号： H03K19/00361

摘要： A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’

摘要翻译： 已经开发了用于降低基于PECL的组件中的电压变化的方法。 该方法包括对基于PECL的组件（例如用于PLL的接收机电路）加电，以及在PECL电源的电源端子上激活或插入分流电阻。 分流电阻与基于PECL的部件并联插入，并且是可控制的，使得电阻可以被选择性地“接通”和/或“关闭”。

公开(公告)号：US06753740B2

公开(公告)日：2004-06-22

申请号：US10147593

申请日：2002-05-17

申请人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03B100

CPC分类号： H03L7/0893 ,  H03L7/18

摘要： A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

摘要翻译： 提供了一种用于锁相环偏置发生器的后制造控制的校准和调节系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造了锁相环之后实现期望的锁相环性能特性。 可以存储和随后读取偏置发生器输出中期望的调节量的代表值来调整锁相环。