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80 条记录 (耗时 0.023 秒)

    Reducing voltage variation in a phase locked loop
    1.
    发明授权
    Reducing voltage variation in a phase locked loop 有权
    降低锁相环中的电压变化

    公开(公告)号：US06639439B2

    公开(公告)日：2003-10-28

    申请号：US09981385

    申请日：2001-10-16

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

    IPC分类号： H03L706

    CPC分类号： H03L7/06

    摘要： A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’

    摘要翻译： 已经开发了一种用于降低锁相环电源系统中的电压变化的方法。 该方法包括上电锁相环，并在电源端子上激活或插入分流电阻。 分流电阻与锁相环平行插入，并且可控制，使得电阻可以选择性地“接通”和/或“关闭”。

    Reducing PECL voltage variation
    2.
    发明授权
    Reducing PECL voltage variation 有权
    降低PECL电压变化

    公开(公告)号：US06556041B1

    公开(公告)日：2003-04-29

    申请号：US09978869

    申请日：2001-10-16

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Dean Liu ,  Brian Amick

    IPC分类号： H03K1716

    CPC分类号： H03K19/00361

    摘要： A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’

    摘要翻译： 已经开发了用于降低基于PECL的组件中的电压变化的方法。 该方法包括对基于PECL的组件（例如用于PLL的接收机电路）加电，以及在PECL电源的电源端子上激活或插入分流电阻。 分流电阻与基于PECL的部件并联插入，并且是可控制的，使得电阻可以被选择性地“接通”和/或“关闭”。

    Programmable leakage current offset for delay locked loop
    3.
    发明授权
    Programmable leakage current offset for delay locked loop 有权
    用于延迟锁定环路的可编程漏电流补偿

    公开(公告)号：US06573770B1

    公开(公告)日：2003-06-03

    申请号：US10230726

    申请日：2002-08-29

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Brian W. Amick ,  Dean Liu

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Brian W. Amick ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0812 ,  H03L7/0891

    摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor in the delay locked loop. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated.

    摘要翻译： 提供了延迟锁定环路漏电流的制造后调整方法和装置。 调整系统包括调整电路，调整漏电流补偿电路以补偿延迟锁定环中的电容器的漏电流。 电容器连接到延迟锁定环路的控制电压。 在延迟锁定环路中的这种对漏电流的控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路工作特性。

    Deskewing global clock skew using localized DLLs
    4.
    发明授权
    Deskewing global clock skew using localized DLLs 有权
    使用本地化DLL来消除全局时钟偏移

    公开(公告)号：US06686785B2

    公开(公告)日：2004-02-03

    申请号：US09975359

    申请日：2001-10-11

    申请人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    发明人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    IPC分类号： H03L706

    CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

    摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

    摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。

    Programmable current source adjustment of leakage current for delay locked loop
    5.
    发明授权
    Programmable current source adjustment of leakage current for delay locked loop 有权
    用于延迟锁定环路的可编程电流源调节漏电流

    公开(公告)号：US06570420B1

    公开(公告)日：2003-05-27

    申请号：US10230649

    申请日：2002-08-29

    申请人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

    发明人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0891 ,  H03L7/0812

    摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

    摘要翻译： 提供了延迟锁定环路漏电流的制造后调整方法和装置。 调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。 电容器连接到延迟锁定环路的控制电压。 可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。 可编程电流源由组合逻辑电路选择性地调节。 对延迟锁定环路中的漏电流的这种控制允许设计者在制造可调延迟锁定环路之后实现期望的延迟锁定环路工作特性。

    Method and apparatus to store delay locked loop biasing parameters
    9.
    发明授权
    Method and apparatus to store delay locked loop biasing parameters 有权
    存储延迟锁定环偏置参数的方法和装置

    公开(公告)号：US07251305B2

    公开(公告)日：2007-07-31

    申请号：US10147838

    申请日：2002-05-17

    申请人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude R. Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0812

    摘要： A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

    摘要翻译： 提供了一种用于延迟锁定环偏置发生器的后制造控制的校准和调整系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。 可以存储和随后读取偏置 - 发生器输出中期望的调节量的代表值来调整延迟锁定环。