公开(公告)号：US20160072484A1

公开(公告)日：2016-03-10

申请号：US14481269

申请日：2014-09-09

Applicant: Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

Inventor： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/0372

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract translation: 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

公开(公告)号：US07420401B2

公开(公告)日：2008-09-02

申请号：US11453324

申请日：2006-06-14

Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

IPC: H03K3/02

CPC classification number: H03K19/1732 ,  G06F1/22

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

公开(公告)号：US20070290731A1

公开(公告)日：2007-12-20

申请号：US11453324

申请日：2006-06-14

Applicant: Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

Inventor： Colin MacDonald ,  Alan J. Carlin ,  Chris C. Dao

IPC: H03K3/02

CPC classification number: H03K19/1732 ,  G06F1/22

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract translation: 集成电路配置有用于指定集成电路内的电路的复位配置向量的引脚。 检测并利用耦合到引脚的低成本外部电阻器的电阻值来识别配置。 集成电路上的逻辑检测并利用电阻值对查找表中的配置向量进行索引。 然后根据索引的配置向量配置集成电路。

公开(公告)号：US06999627B2

公开(公告)日：2006-02-14

申请号：US10025290

申请日：2001-12-19

Applicant: Colin MacDonald ,  Tamas Kovacs

Inventor： Colin MacDonald ,  Tamas Kovacs

IPC: G06K9/36

CPC classification number: G06T9/004 ,  H04N19/42 ,  H04N19/44 ,  H04N19/91

Abstract: Embodiments of the present invention relate to deterministic prediction in an image processing system. One aspect relates to an image processing system having a deterministic prediction decode unit for predicting individual pixels of an image based on a predetermined deterministic prediction algorithm. The deterministic prediction decode unit includes a look-up table, organized into four spatial phases, for storing values to be used by the predetermined deterministic prediction algorithm when converting a relatively low resolution image to a relatively higher resolution image. A prediction is made for a target pixel by accessing at least two of the four spatial phases of the look-up table to read at least two possible values of the target pixel. In one embodiment, the value of two target pixels can be provided within a same clock period, thus allowing for the decoding of two spatial phases with each access to the look-up table.