公开(公告)号：US09153212B2

公开(公告)日：2015-10-06

申请号：US13850548

申请日：2013-03-26

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Albert C. Kuo

IPC: G09G5/395 ,  G06F3/14 ,  G09G5/00 ,  G09G5/393

CPC classification number: G09G5/395 ,  G06F3/14 ,  G09G5/001 ,  G09G5/393 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为响应于检测输出帧中的静态内容而压缩输出帧并将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。

公开(公告)号：US20140333643A1

公开(公告)日：2014-11-13

申请号：US13889816

申请日：2013-05-08

Applicant: APPLE INC.

Inventor： Albert C. Kuo ,  Peter F. Holland

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G5/001 ,  G09G2360/12

Abstract: A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state.

Abstract translation: 一种用于从显示控制器管线有效地调度存储器访问请求的系统和方法。 显示控制器监视内部像素处理流水线中的行缓冲器中的数据量。 在向存储器控制器发出存储器请求之前，显示控制器等待直到给定行缓冲器中的数据量已经下降到等于由内部像素处理流水线呈现的区域的像素宽度的量的量。 当存储器控制器不处理接收到的存储器请求时，存储器控制器转换到低功率状态。