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公开(公告)号：US11978385B2
公开(公告)日：2024-05-07
申请号：US17889242
申请日：2022-08-16
Applicant: Apple Inc.
Inventor： Yao Shi , Wei H Yao , Hyunwoo Nho , Jie Won Ryu , Kingsuk Brahma , Li-Xuan Chuo , Hyunsoo Kim , Myungjoon Choi , Ce Zhang , Alex H Pai , Shengkui Gao , Rungrot Kitsomboonloha , Shatam Agarwal , Vehbi Calayir , Chaohao Wang , Steven N Hanna , Pei-En Chang
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G3/2007 , G09G2310/0291 , G09G2320/0223 , G09G2320/0233 , G09G2330/021 , G09G2360/16
Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.
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公开(公告)号：US10955947B2
公开(公告)日：2021-03-23
申请号：US15493791
申请日：2017-04-21
Applicant: Apple Inc.
Inventor： Patrick Bennett , Byung Duk Yang , Chun-Yao Huang , Hao-Lin Chiu , Ivan Knez , Peien Chang , Rungrot Kitsomboonloha , Shih-Chang Chang , Shinya Ono , Szuhsien Lee
Abstract: A touch sensor panel comprising a first touch node electrode of a plurality of touch node electrodes, the first touch node electrode coupled to a first sense connection comprising a first set of traces, the first sense connection configured to have a first resistance per unit length that varies along a length of the first sense connection, and a second touch node electrode of the plurality of touch node electrodes, the second touch node electrode coupled to a second sense connection comprising a second set of traces, the second sense connection configured to have a second resistance per unit length that varies along a length of the second sense connection differently than the first resistance per unit length varies along the length of the first sense connection. An effective resistance of the first sense connection and the second sense connection are equal.
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公开(公告)号：US10037738B2
公开(公告)日：2018-07-31
申请号：US14862071
申请日：2015-09-22
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang , Szu-Hsien Lee
IPC: G09G3/36 , G09G3/3225 , G09G3/20
CPC classification number: G09G3/3674 , G09G3/20 , G09G3/3225 , G09G3/3648 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291
Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.
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公开(公告)号：US20170004790A1
公开(公告)日：2017-01-05
申请号：US14862071
申请日：2015-09-22
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang , Szu-Hsien Lee
CPC classification number: G09G3/3674 , G09G3/20 , G09G3/3225 , G09G3/3648 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291
Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.
Abstract translation: 提供了一种显示器，其包括用于向显示像素提供数据和栅极线信号的显示像素阵列和栅极驱动器电路。 栅极驱动器电路可以包括产生栅极线信号的栅极驱动器电路。 栅极驱动器电路可以包括至少缓冲晶体管，耦合到缓冲晶体管的自举电容器，与缓冲晶体管串联耦合的下拉晶体管，以及耦合到下拉晶体管的栅极的隔离晶体管。 缓冲晶体管可以直接接收第一时钟信号，而隔离晶体管可以直接接收与第一时钟信号互补的第二时钟信号。 下拉晶体管实质上大于缓冲晶体管。 缓冲晶体管基本上大于隔离晶体管。 如此配置，时钟负载最小化，而下拉晶体管的尺寸设置为提供所需的下降时间性能。
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公开(公告)号：US20160293081A1
公开(公告)日：2016-10-06
申请号：US14677531
申请日：2015-04-02
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chun-Yao Huang , Shih Chang Chang , Szu-Hsien Lee
CPC classification number: G06F3/0416 , G09G3/3677 , G09G2310/0202 , G09G2310/0218 , G09G2310/0267 , G09G2320/043
Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.
Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器电路块，每个栅极驱动器电路具有耦合到相应的一条栅极线的输出。 每个块的栅极驱动器电路被耦合在链中以形成移位寄存器。 每个块具有本地块级门控起始脉冲发生器。 显示驱动器电路具有显示驱动器电路，其向每个本地块级门控起始脉冲发生器提供栅极起始脉冲时钟。 局部块电平门起始脉冲发生器产生施加到每个移位寄存器中的第一栅极驱动器电路的栅极起始脉冲。 当期望实现帧内暂停时，显示驱动器电路可以延迟门启动脉冲时钟。
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Patent Agency Ranking
公开(公告)号：US20230084423A1
公开(公告)日：2023-03-16
申请号：US17853649
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Myungjoon Choi , Jie Won Ryu , Hyunwoo Nho , Xiaokai Li , Kaikai Guo , Szu-Hsien Lee , Rungrot Kitsomboonloha , Pei-En Chang , Amit Nayyar , Vehbi Calayir
Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.
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公开(公告)号：US11605330B1
公开(公告)日：2023-03-14
申请号：US17853649
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Myungjoon Choi , Jie Won Ryu , Hyunwoo Nho , Xiaokai Li , Kaikai Guo , Szu-Hsien Lee , Rungrot Kitsomboonloha , Pei-En Chang , Amit Nayyar , Vehbi Calayir
Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.
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公开(公告)号：US11580905B2
公开(公告)日：2023-02-14
申请号：US17749045
申请日：2022-05-19
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chin-Wei Lin , Shinya Ono , Gihoon Choo , Hao-Lin Chiu , Kyung Wook Kim , Pei-En Chang , Szu-Hsien Lee , Zino Lee
IPC: G09G3/3225
Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
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公开(公告)号：US20210305353A1
公开(公告)日：2021-09-30
申请号：US17143939
申请日：2021-01-07
Applicant: Apple Inc.
Inventor： Shinya Ono , Chin-Wei Lin , Akira Matsudaira , Jiun-Jye Chang , Jung Yen Huang , Pei-En Chang , Rungrot Kitsomboonloha , Szu-Hsien Lee
IPC: H01L27/32 , G09G3/3266 , G09G3/3225
Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.
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公开(公告)号：US09424793B2
公开(公告)日：2016-08-23
申请号：US14726312
申请日：2015-05-29
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Kwang Soon Park , Chin-Wei Lin , Chun-Yao Huang , Shih Chang Chang , Szu-Hsien Lee
CPC classification number: G09G3/3648 , G06F3/0412 , G06F3/0416 , G09G2300/0408 , G09G2300/0842
Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.
Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。
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