公开(公告)号：US12096657B2

公开(公告)日：2024-09-17

申请号：US17504230

申请日：2021-10-18

Applicant: Apple Inc.

Inventor： Jung Yen Huang ,  Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Cheng Min Hu ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Gihoon Choo ,  Jiun-Jye Chang ,  Po-Chun Yeh ,  Shih Chang Chang ,  Yu-Wen Liu ,  Zino Lee

IPC: H01L27/32 ,  H01L29/66 ,  H01L29/786 ,  H10K59/121 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H01L29/66742 ,  H01L29/7869 ,  H10K59/1216 ,  H10K59/1201

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

公开(公告)号：US20210193049A1

公开(公告)日：2021-06-24

申请号：US17075587

申请日：2020-10-20

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Jung Yen Huang

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/20

Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

公开(公告)号：US12148390B2

公开(公告)日：2024-11-19

申请号：US17962239

申请日：2022-10-07

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Jung Yen Huang

IPC: G09G3/3266 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3291

Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

公开(公告)号：US20230035245A1

公开(公告)日：2023-02-02

申请号：US17962239

申请日：2022-10-07

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Jung Yen Huang

IPC: G09G3/3266 ,  G09G3/20 ,  G09G3/3291

Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

公开(公告)号：US20180061867A1

公开(公告)日：2018-03-01

申请号：US15344045

申请日：2016-11-04

Applicant: Apple Inc.

Inventor： Chih Pang Chang ,  Jung-Fang Chang ,  ChinWei Hu ,  Te-Hua Teng ,  Jung Yen Huang ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Ching-Sang Chuang ,  Hung-Che Ting ,  Lungpao Hsin

IPC: H01L27/12

CPC classification number: H01L27/1251 ,  H01L27/1225

Abstract: Hybrid silicon TFT and oxide TFT structures and methods of formation are described. In an embodiment, a protection layer is formed over a semiconductor oxide channel layer of the oxide TFT to protect the semiconductor oxide channel layer during a cleaning operation of the silicon TFT.

公开(公告)号：US20250081730A1

公开(公告)日：2025-03-06

申请号：US18755498

申请日：2024-06-26

Applicant: Apple Inc.

Inventor： Andrew Lin ,  Alper Ozgurluk ,  Chao Liang Chien ,  Cheuk Chi Lo ,  Chia-Yu Chen ,  Chien-Chung Wang ,  Chih Pang Chang ,  Chih-Hung Yu ,  Chih-Wei Chang ,  Chin Wei Hsu ,  ChinWei Hu ,  Chun-Kai Tzeng ,  Chun-Ming Tang ,  Chun-Yao Huang ,  Hung-Che Ting ,  Jung Yen Huang ,  Lungpao Hsin ,  Shih Chang Chang ,  Tien-Pei Chou ,  Wen Sheng Lo ,  Yu-Wen Liu ,  Yung Da Lai

IPC: H10K59/121 ,  H10K59/131

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

公开(公告)号：US20240210995A1

公开(公告)日：2024-06-27

申请号：US18483653

申请日：2023-10-10

Applicant: Apple Inc.

Inventor： Prashant Mandlik ,  Bhadrinarayana Lalgudi Visweswaran ,  Mahendra Chhabra ,  Chia-Hao Chang ,  Shiyi Liu ,  Siddharth Harikrishna Mohan ,  Zhen Zhang ,  Han-Chieh Chang ,  Yi Qiao ,  Yue Cui ,  Tyler R Kakuda ,  Michael Vosgueritchian ,  Sudirukkuge T. Jinasundera ,  Warren S Rieutort-Louis ,  Tsung-Ting Tsai ,  Jae Won Choi ,  Jiun-Jye Chang ,  Jean-Pierre S Guillou ,  Rui Liu ,  Po-Chun Yeh ,  Chieh Hung Yang ,  Ankit Mahajan ,  Takahide Ishii ,  Pei-Ling Lin ,  Pei Yin ,  Gwanwoo Park ,  Markus Einzinger ,  Martijn Kuik ,  Abhijeet S Bagal ,  Kyounghwan Kim ,  Jonathan H Beck ,  Chiang-Jen Hsiao ,  Chih-Hao Kung ,  Chih-Lei Chen ,  Chih-Yu Chung ,  Chuan-Jung Lin ,  Jung Yen Huang ,  Kuan-Chi Chen ,  Shinya Ono ,  Wei Jung Hsieh ,  Wei-Chieh Lin ,  Yi-Pu Chen ,  Yuan Ming Chiang ,  An-Di Sheu ,  Chi-Wei Chou ,  Chin-Fu Lee ,  Ko-Wei Chen ,  Kuan-Yi Lee ,  Weixin Li ,  Shin-Hung Yeh ,  Shyuan Yang ,  Themistoklis Afentakis ,  Asli Sirman ,  Baolin Tian ,  Han Liu

IPC: G06F1/16 ,  H10K59/131 ,  H10K59/40 ,  H10K77/10

CPC classification number: G06F1/1652 ,  H10K59/131 ,  H10K59/40 ,  H10K77/111 ,  H10K2102/311

Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.

公开(公告)号：US20170294499A1

公开(公告)日：2017-10-12

申请号：US15268106

申请日：2016-09-16

Applicant: Apple Inc.

Inventor： Chang Ming Lu ,  Chia-Yu Chen ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Hung-Che Ting ,  Jung Yen Huang ,  Sheng Hui Shen ,  Shih Chang Chang ,  Tsung-Hsiang Shih ,  Yu-Wen Liu ,  Yu Hung Chen ,  Kai-Chieh Wu ,  Lun Tsai ,  Takahide Ishii ,  Chung-Wang Lee ,  Hsing-Chuan Wang ,  Chin Wei Hsu ,  Fu-Yu Teng

IPC: H01L27/32 ,  H01L51/56 ,  H01L23/532 ,  H01L21/027 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/77

Abstract: A component such as a display may have a substrate and thin-film circuitry on the substrate. The thin-film circuitry may be used to form an array of pixels for a display or other circuit structures. Metal traces may be formed among dielectric layers in the thin-film circuitry. Metal traces may be provided with insulating protective sidewall structures. The protective sidewall structures may be formed by treating exposed edge surfaces of the metal traces. A metal trace may have multiple layers such as a core metal layer sandwiched between barrier metal layers. The core metal layer may be formed from a metal that is subject to corrosion. The protective sidewall structures may help prevent corrosion in the core metal layer. Surface treatments such as oxidation, nitridation, and other processes may be used in forming the protective sidewall structures.

公开(公告)号：US20220181418A1

公开(公告)日：2022-06-09

申请号：US17504230

申请日：2021-10-18

Applicant: Apple Inc.

Inventor： Jung Yen Huang ,  Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Cheng Min Hu ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Gihoon Choo ,  Jiun-Jye Chang ,  Po-Chun Yeh ,  Shih Chang Chang ,  Yu-Wen Liu ,  Zino Lee

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

公开(公告)号：US20210305353A1

公开(公告)日：2021-09-30

申请号：US17143939

申请日：2021-01-07

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Jiun-Jye Chang ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3225

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.