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    Displays with Supplemental Loading Structures
    12.
    发明申请
    Displays with Supplemental Loading Structures 审中-公开

    公开(公告)号：US20200013360A1

    公开(公告)日：2020-01-09

    申请号：US16518527

    申请日：2019-07-22

    Applicant: Apple Inc.

    Inventor： Shin-Hung Yeh ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

    IPC: G09G3/36 ,  G09G3/00 ,  H01L27/12 ,  G02F1/1362

    Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

    SYSTEMS AND METHODS FOR IMPROVING ENERGY EFFICIENCY OF GATE DRIVER CIRCUITS
    14.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVING ENERGY EFFICIENCY OF GATE DRIVER CIRCUITS 有权
    提高门驱动电路能源效率的系统和方法

    公开(公告)号：US20160094215A1

    公开(公告)日：2016-03-31

    申请号：US14502883

    申请日：2014-09-30

    Applicant: APPLE INC.

    Inventor： Ting-Kuo Chang ,  Abbas Jamshidi-Roudbari ,  Shin-Hung Yeh

    IPC: H03K17/56 ,  G09G3/36

    CPC classification number: H03K17/56 ,  G09G3/3677

    Abstract: A gate drive circuit may include a latch circuit, a first transmission gate, and a second transmission gate. The first transmission gate and the second transmission gate may both be directly coupled to the latch circuit and may be directly coupled to a first gate line and a second gate line, respectively. The latch circuit may receive an electrical signal from a third gate line adjacent to the second gate line, such that the electrical signal is configured to reset a state of the latch circuit.

    Abstract translation: 栅极驱动电路可以包括锁存电路，第一传输门和第二传输门。 第一传输门和第二传输门都可以直接耦合到锁存电路，并且可以分别直接耦合到第一栅极线和第二栅极线。 锁存电路可以从与第二栅极线相邻的第三栅极线接收电信号，使得电信号被配置为复位锁存电路的状态。

    Displays with Data Lines that Accommodate Openings
    16.
    发明申请
    Displays with Data Lines that Accommodate Openings 有权

    公开(公告)号：US20220066272A1

    公开(公告)日：2022-03-03

    申请号：US17525118

    申请日：2021-11-12

    Applicant: Apple Inc.

    Inventor： Shin-Hung Yeh ,  Warren S. Rieutort-Louis ,  Abbas Jamshidi Roudbari ,  Chien-Ya Lee ,  Lun Tsai

    IPC: G02F1/1362 ,  G09G3/20 ,  H01L27/32

    Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

    High Frame Rate Display
    17.
    发明申请
    High Frame Rate Display 有权

    公开(公告)号：US20210210022A1

    公开(公告)日：2021-07-08

    申请号：US17206425

    申请日：2021-03-19

    Applicant: Apple Inc.

    Inventor： Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Tsung-Ting Tsai ,  Warren S. Rieutort-Louis ,  Shinya Ono ,  Shin-Hung Yeh ,  Chien-Ya Lee ,  Shyuan Yang

    IPC: G09G3/3275 ,  G09G3/3233 ,  G09G3/3266

    Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

    Displays with supplemental loading structures
    18.
    发明授权
    Displays with supplemental loading structures 有权

    公开(公告)号：US10360862B2

    公开(公告)日：2019-07-23

    申请号：US15980437

    申请日：2018-05-15

    Applicant: Apple Inc.

    Inventor： Shin-Hung Yeh ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

    IPC: G09G3/36 ,  G02F1/1362 ,  G09G3/00 ,  H01L27/12

    Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

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