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公开(公告)号:US12125736B2
公开(公告)日:2024-10-22
申请号:US18103811
申请日:2023-01-31
IPC分类号: H01L21/683 , G09G3/32 , H01L25/16
CPC分类号: H01L21/6835 , G09G3/32 , H01L25/167 , G09G2300/0404
摘要: Provided are a display panel and a transfer method. The display panel includes: an array substrate, where the array substrate includes a base substrate, and the base substrate comprises a plurality of sub-pixel setting regions arranged in an array; an insulating layer located on a side of the pixel driving circuit array facing away from the base substrate, where the pixel driving circuit array includes pixel driving circuits arranged in an array; the insulating layer forms accommodating grooves respectively within the plurality of sub-pixel setting regions; and the pixel driving circuits are disposed in one-to-one correspondence with the accommodating grooves; and data lines and heating lines, where each of the data lines is electrically connected to a respective column of pixel driving circuits among a plurality of columns of pixel driving circuits arranged in the array.
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公开(公告)号:US12038659B2
公开(公告)日:2024-07-16
申请号:US18182222
申请日:2023-03-10
申请人: Apple Inc.
IPC分类号: G02F1/1362 , G09G3/20 , H10K59/122 , H10K59/131
CPC分类号: G02F1/136286 , G09G3/20 , H10K59/122 , H10K59/131 , G02F1/13629 , G09G2300/0404 , G09G2300/0426
摘要: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.
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公开(公告)号:US20230186813A1
公开(公告)日:2023-06-15
申请号:US18164557
申请日:2023-02-03
申请人: Innolux Corporation
发明人: Yu-Chia Huang , Yuan-Lin Wu , Tsung-Han Tsai , Kuan-Feng Lee
IPC分类号: G09G3/20
CPC分类号: G09G3/20 , G09G2300/0404 , G09G2310/0275
摘要: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area .
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公开(公告)号:US20180357983A1
公开(公告)日:2018-12-13
申请号:US16049108
申请日:2018-07-30
申请人: Sony Corporation
发明人: Akira Yumoto
IPC分类号: G09G5/18 , G09G3/3225 , G09G3/3233 , G09G3/32
CPC分类号: G09G5/18 , G09G3/32 , G09G3/3225 , G09G3/3233 , G09G2300/0404 , G09G2300/043 , G09G2300/0819 , G09G2300/0861 , G09G2300/0866 , G09G2310/0267 , G09G2320/0233 , G09G2320/043
摘要: Herein disclosed an image display including: row scan lines configured to supply a control signal; column signal lines configured to supply a video signal; and pixel circuits configured to be disposed at intersections between the scan lines and the signal lines, wherein each of the pixel circuits has at least a drive transistor, a sampling transistor connected to a gate of the drive transistor, a capacitive part connected between the gate and a source of the drive transistor, and a light-emitting element connected to the source of the drive transistor.
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公开(公告)号:US20180211629A1
公开(公告)日:2018-07-26
申请号:US15500156
申请日:2017-01-19
发明人: Mian Zeng
IPC分类号: G09G3/36
CPC分类号: G09G3/3677 , G09G3/36 , G09G2300/0404 , G09G2300/0408 , G09G2310/0267 , G09G2310/0281 , G09G2310/0286 , G09G2310/08
摘要: Disclosed are a double-side gate driver on array circuit, a liquid crystal display panel, and a driving method. A technical problem to be solved is that double-side drive design which includes a GOA circuit unit having two pull-down holding parts cannot meet requirements for narrow-bezel display panel design when a narrow-bezel, large-size display device is manufactured. A solution of the double-side gate driver on array circuit is: GOA units of two opposite sides in a same row share one group of pull-down holding parts.
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公开(公告)号:US20180190219A1
公开(公告)日:2018-07-05
申请号:US15844750
申请日:2017-12-18
发明人: Hiroyuki MIYAKE
IPC分类号: G09G3/36
CPC分类号: G09G3/3614 , G02F1/13306 , G02F1/136213 , G02F1/1368 , G09G3/3611 , G09G3/3655 , G09G5/18 , G09G2300/0404 , G09G2300/0408 , G09G2300/0426 , G09G2300/0876 , G09G2320/10
摘要: An object is to suppress deterioration of a displayed image even when a refresh rate is reduced in displaying a still image. A liquid crystal display device includes a pixel transistor electrically connected to a pixel electrode, and a capacitor having one electrode electrically connected to the pixel electrode and the other electrode electrically connected to a capacitor line. The pixel transistor is turned on and a voltage based on an image signal is supplied to the pixel electrode, and then, the pixel transistor is turned off so that a holding period during which the pixel electrode holds the voltage based on the image signal starts. A holding signal corresponding to change of the voltage based on the image signal in the pixel electrode in the holding period is supplied to the capacitor line so that a potential of the pixel electrode is constant.
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公开(公告)号:US20180166014A1
公开(公告)日:2018-06-14
申请号:US15879899
申请日:2018-01-25
申请人: JOLED INC.
发明人: Hiroshi TAKAHARA , Hitoshi TSUGE
IPC分类号: G09G3/3241 , H01L51/52 , G09G3/20 , G09G3/32 , G09G3/3233 , G09G3/325 , G09G3/3258 , G09G3/3266 , G09G3/3275 , H01L27/12 , H01L27/32 , G09G5/02 , H01L29/786
CPC分类号: G09G3/3241 , G09G3/2003 , G09G3/2007 , G09G3/32 , G09G3/3233 , G09G3/325 , G09G3/3258 , G09G3/3266 , G09G3/3275 , G09G5/02 , G09G2300/0404 , G09G2300/0413 , G09G2300/0809 , G09G2300/0814 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/0205 , G09G2310/0218 , G09G2310/0248 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/0289 , G09G2310/08 , G09G2320/0247 , G09G2320/0257 , G09G2320/0261 , G09G2320/043 , G09G2320/06 , G09G2320/0606 , G09G2320/0626 , G09G2320/0646 , G09G2320/0653 , H01L27/124 , H01L27/1251 , H01L27/1255 , H01L27/127 , H01L27/156 , H01L27/3211 , H01L27/3216 , H01L27/3244 , H01L27/3262 , H01L27/3265 , H01L29/78645 , H01L29/78672 , H01L33/56 , H01L33/58 , H01L51/525 , H01L51/5253 , H01L51/5259 , H01L51/5281
摘要: An electroluminescent (EL) display apparatus and method are provided. A display screen includes pixels. A pixel circuit of each of pixel includes, in part: a first switch transistor on a path through which current flows from a power line through a driving transistor to an EL device; a second switch transistor to supply an image signal to the driving transistor; and a third switch transistor for initially resetting the pixel circuit before the second switch transistor supplies the image signal. A gate terminal of the first switch transistor is connected to a first gate driver circuit. Gate terminals of the second and third switch transistors are connected to a second gate driver circuit, which includes a second gate signal line connected to both the gate terminal of the second switch transistor of a Nth row and the gate terminal of the third switch transistor of a (N+1)th row.
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公开(公告)号:US09990904B2
公开(公告)日:2018-06-05
申请号:US15393274
申请日:2016-12-29
申请人: E Ink Holdings Inc.
发明人: Ya-Chen Huang , Puru Howard Shieh , Ni-Yeh Wu , Pei-Lin Huang , Chi-Ming Wu
CPC分类号: G09G5/10 , G02F1/136286 , G02F2001/13456 , G02F2001/13629 , G09G3/20 , G09G3/2092 , G09G2300/0404 , G09G2300/0413 , G09G2300/0426 , G09G2300/0439 , G09G2300/08 , G09G2310/0218 , G09G2320/0233
摘要: A pixel array including first signal lines, second signal lines, active elements, pixel electrodes and selection lines is provided. The second signal lines and the selection lines are intersected with the first signal lines respectively. Each first signal line has a bridge point at an intersection with the one of the selection lines. At least one of the selection lines is disposed between two neighboring second signal lines. Amounts of the first signal lines and the selection lines are larger than an amount of the second signal lines respectively, and an amount of second signal lines intersected with a connection line between the bridge point of the ith first signal line and the bridge point of the (i+1)th first signal line is one, i=1 to N, and N is the amount of the first signal lines.
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公开(公告)号:US09984635B2
公开(公告)日:2018-05-29
申请号:US14574260
申请日:2014-12-17
发明人: Dong Eup Lee
CPC分类号: G09G3/3611 , G09G3/2085 , G09G2300/0404 , G09G2310/0281 , G09G2310/0283
摘要: Provided is a display device including a display panel having a display area including a plurality of pixel columns, the display device including: a first pixel column including i pixels (i is a natural number) from among the plurality of pixel columns; a second pixel column including j pixels (j is a different natural number than i) from among the plurality of pixel columns; a first data line connected to the i pixels in the first pixel column, and to k pixels (k is a smaller natural number than j) from among the j pixels in the second pixel column; a second data line connected to j minus k (j-k) pixels from among the j pixels in the second pixel column; and gate lines connected to pixels in the first pixel column and the second pixel column.
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公开(公告)号:US09978329B2
公开(公告)日:2018-05-22
申请号:US15300000
申请日:2016-10-21
发明人: Hiroyuki Miyake , Kouhei Toyotaka
CPC分类号: G09G3/3677 , G09G3/3266 , G09G3/3648 , G09G3/3696 , G09G5/18 , G09G2300/0404 , G09G2300/0413 , G09G2310/0205 , G09G2310/0286 , G09G2310/0291 , G11C19/28 , H03K3/356026
摘要: Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.
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