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    Light-emitting diode display with reduced leakage
    1.
    发明授权
    Light-emitting diode display with reduced leakage 有权

    公开(公告)号：US10311782B2

    公开(公告)日：2019-06-04

    申请号：US15246345

    申请日：2016-08-24

    Applicant: Apple Inc.

    Inventor： Warren S. Rieutort-Louis ,  Keitaro Yamashita ,  Tsung-Ting Tsai ,  Yun Wang ,  Ting-Kuo Chang ,  Cheng-Ho Yu ,  Shinya Ono

    IPC: G09G3/3233 ,  G09G3/3266

    Abstract: An organic light-emitting diode display may contain an array of display pixels. Each display pixel may have a respective organic light-emitting diode that is controlled by a drive transistor. At low temperatures, it may be necessary to increase the amount of current through an organic light-emitting diode to achieve a desired luminance level. In order to increase the current through the light-emitting diode, the ground voltage level may be lowered. However, this may lead to thin-film transistors within the pixel leaking, which may result in undesirable display artifacts such as bright dots being displayed in a dark image. In order to prevent leakage in the transistors, the transistors may be coupled to separate reference voltage supplies or separate control lines. Additionally, the transistors may be positioned to minimize leakage even at low ground voltage levels.

    Displays with gate driver circuitry for discharging display pixels
    3.
    发明授权
    Displays with gate driver circuitry for discharging display pixels 有权

    公开(公告)号：US10078405B2

    公开(公告)日：2018-09-18

    申请号：US14988586

    申请日：2016-01-05

    Applicant: Apple Inc.

    Inventor： Abbas Jamshidi Roudbari ,  Keitaro Yamashita

    IPC: G06F3/044

    CPC classification number: G06F3/044 ,  G06F3/0418

    Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The gate driver circuitry may include gate drivers connected in a chain. A given one of the gate drivers may include a set-reset latch. The set-reset latch may have a set input and a reset input. A logic gating circuit such as a logic NOR gate may have an output directly connected to the set input. The NOR gate may have a first input coupled to an output of a preceding gate driver in the chain and a second input coupled to an output of a succeeding gate driver. The reset input may be coupled to the output of the preceding gate driver. Gate line output signals may be simultaneously asserted for each of the drivers without generating unstable scenarios where logic high signals are provided to the set and reset inputs.

    Displays with multiple scanning modes
    5.
    发明授权
    Displays with multiple scanning modes 有权

    公开(公告)号：US10546540B1

    公开(公告)日：2020-01-28

    申请号：US16577597

    申请日：2019-09-20

    Applicant: Apple Inc.

    Inventor： Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Shin-Hung Yeh ,  Tsung-Ting Tsai ,  Shih-Chang Chang ,  Ting-Kuo Chang ,  Ki Yeol Byun ,  Warren S. Rieutort-Louis

    IPC: G09G3/3266

    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.

    Devices and methods for preventing image artifacts on touch sensitive electronic displays
    6.
    发明授权
    Devices and methods for preventing image artifacts on touch sensitive electronic displays 有权

    公开(公告)号：US10042409B2

    公开(公告)日：2018-08-07

    申请号：US14986371

    申请日：2015-12-31

    Applicant: Apple Inc.

    Inventor： Keitaro Yamashita ,  Majid Gharghi ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari

    IPC: G06F1/32 ,  G06F3/041 ,  G06F3/044 ,  G09G3/20

    Abstract: Methods and devices useful in discharging an aberrant charge on a touch sensitive display of an electronic device are provided. By way of example, a an electronic device includes a power management and control circuitry configured to receive a first voltage signal and a second voltage signal from a display subsystem of a display of the electronic device, receive a third voltage signal from a touch subsystem of the display, provide a power signal to the display subsystem to activate the display subsystem when the display is determined to be in a temporarily inactive state. Providing the power signal to the display subsystem comprises discharging an aberrant charge based on the third voltage signal.

    Display driver circuitry with balanced stress
    8.
    发明授权
    Display driver circuitry with balanced stress 有权

    公开(公告)号：US09842551B2

    公开(公告)日：2017-12-12

    申请号：US14549475

    申请日：2014-11-20

    Applicant: Apple Inc.

    Inventor： Keitaro Yamashita ,  Ting-Kuo Chang

    IPC: G09G3/36 ,  G11C19/28 ,  G09G3/20

    CPC classification number: G09G3/3611 ,  G09G3/20 ,  G09G3/3677 ,  G09G2300/0439 ,  G09G2310/0224 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/04 ,  G11C19/28

    Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse is that received through a demultiplexing circuit. In another suitable embodiment, the gate driver circuit may include analog or digital gate driver units that include control circuits for selectively (dis)charging internal nodes in the gate driver circuit so as to balance the amount of stress that is experienced by a drive transistor in gate driver units at or near an IFP row and the amount of stress that is experienced by the remaining gate driver units.

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