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1.发明公开公开(公告)号：US20240356544A1
公开(公告)日：2024-10-24
申请号：US18138008
申请日：2023-04-21
申请人： XILINX, INC.
摘要： Embodiments herein describe an integrated circuit (IC) device that includes a multi-protocol, multi-cast, and multi-root network-on-chip (NoC) with dynamic resource allocation (DFxNoC). A DFxNoC may include a plurality of end-points (EPs) that include functional circuitry, first and second root devices, and a bus network that includes multi-port switch circuits and a network of fixed links amongst the multi-port switch circuits, the root devices, and the EPs, where the root devices output respective first and second clocks, and where the multi-port switch circuits are dynamically configurable to route the first and second clocks to respective first and second selectable sets of one or more of the EPs over the network of fixed links.
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公开(公告)号：US12113532B2
公开(公告)日：2024-10-08
申请号：US18091381
申请日：2022-12-30
发明人： Chih-Yuan Chang , Yu-Te Liao , Wei Cheng Liu
摘要： Pseudo resistor having an auto-tune function automatically calibrates resistance of the pseudo resistor and compensates for DC drift based on an output signal of an electrical circuit to which the pseudo resistor is coupled, as to mitigate signal phenomenon in the output signal caused by PVT variation. The pseudo resistor includes first transistor, second transistor, and adder. The first terminal of the second transistor is coupled to the first terminal of the first transistor and forms a first common node. The control terminal of the first transistor is coupled to the control terminal of the second transistor and forms second common node. The adder is coupled between the first and second common nodes and configured to receive adjustment voltage for generating a bias voltage for controlling the first and second transistors, where the adjustment voltage corresponds to the output signal coupled to the second terminal of the second transistor.
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公开(公告)号：US20240333281A1
公开(公告)日：2024-10-03
申请号：US18598920
申请日：2024-03-07
发明人： Manoj Kumar TIWARI , Sandeep KAUSHIK , Zia PARVEEN
IPC分类号： H03K17/56
CPC分类号： H03K17/56
摘要： Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.
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公开(公告)号：US20240333222A1
公开(公告)日：2024-10-03
申请号：US18616230
申请日：2024-03-26
发明人： Naofumi TAKEZONO
CPC分类号： H03F1/0233 , H03F3/04 , H03K17/56 , H03F2200/105
摘要： A high frequency module includes: a first capacitor C1 having a first end connected to a first signal line; a second capacitor having a first end is connected to a second signal line; a first switch provided between a second end of the first capacitor and a reference potential; a second switch provided between a second end of the second capacitor and the reference potential; an inspection terminal allowing inspection of both the first switch and the second switch; and a resistor connected between a connection point between the first capacitor and the first switch.
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公开(公告)号：US12081207B2
公开(公告)日：2024-09-03
申请号：US18099639
申请日：2023-01-20
IPC分类号： H03K17/56
CPC分类号： H03K17/56
摘要： A semiconductor device includes: a semiconductor body having an active region and a substrate region beneath the active region; a bidirectional switch having first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.
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公开(公告)号：US20240291699A1
公开(公告)日：2024-08-29
申请号：US18655034
申请日：2024-05-03
摘要： An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.
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7.发明公开公开(公告)号：US20240263996A1
公开(公告)日：2024-08-08
申请号：US18425067
申请日：2024-01-29
发明人： SATORU MIKAJIRI
摘要： Output circuit includes differential circuit arranged between first and second power supply lines, and switch and resistor connected in series between the first and second power supply lines. The differential circuit includes first differential output circuit including first positive-side output terminal and first negative-side output terminal, second differential output circuit including second positive-side output terminal and second negative-side output terminal, first output line connecting the first positive-side output terminal and the second positive-side output terminal, and second output line connecting the first negative-side output terminal and the second negative-side output terminal, amplitude modulated signal is output by the first and second output lines. The switch and the resistor suppress change in current flowing between the first and second power supply lines. The output circuit further includes disconnector to disconnect the second differential output circuit from the first differential output circuit.
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公开(公告)号：US12057501B2
公开(公告)日：2024-08-06
申请号：US17653682
申请日：2022-03-07
CPC分类号： H01L29/7813 , H01L29/404 , H01L29/407 , H03K17/56 , H03K2217/0063 , H03K2217/0072
摘要： A semiconductor device of an embodiment includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench on a side of a first face; a first electrode on the side of the first face; a second electrode on the side of the second face; a first gate electrode in the first trench; a first field plate electrode electrically connected to the first electrode in the first trench, a second gate electrode in the second trench; and a second field plate electrode electrically connected to the first electrode in the second trench, a resistance between first electrode and second field plate is different from a resistance between first electrode and the first field plate electrode.
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公开(公告)号：US12028058B2
公开(公告)日：2024-07-02
申请号：US18301184
申请日：2023-04-14
发明人： Amitoj Singh , Tienyu Chang , Siu-Chuang Ivan Lu
CPC分类号： H03K17/56 , H03F3/245 , H04B1/04 , H03F2200/451 , H03K2217/0036
摘要： A shunt switch. In some embodiments, the shunt switch includes a transistor stack including a first transistor and a capacitor. The transistor stack may have a first end terminal and a second end terminal, the first transistor being connected to the first end terminal, the first end terminal being connected to a switching terminal of the shunt switch. The capacitor may have a first terminal connected to the second end terminal of the transistor stack, and a second terminal connected to a low-impedance node.
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公开(公告)号：US12028057B2
公开(公告)日：2024-07-02
申请号：US17951790
申请日：2022-09-23
发明人： Masoud Roham
摘要： A system includes a receiver. The receiver includes an input stage having an input and an output, and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage, and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.
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