公开(公告)号：US11132010B1

公开(公告)日：2021-09-28

申请号：US16905031

申请日：2020-06-18

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia

IPC: H03K5/153 ,  G05F1/46 ,  G01R21/133 ,  G04F10/00

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.

公开(公告)号：US20210167759A1

公开(公告)日：2021-06-03

申请号：US17173055

申请日：2021-02-10

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC: H03K3/037 ,  H03K19/096 ,  H03K3/64

Abstract: A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.

公开(公告)号：US10903824B2

公开(公告)日：2021-01-26

申请号：US16804675

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

公开(公告)号：US20200373915A1

公开(公告)日：2020-11-26

申请号：US16989621

申请日：2020-08-10

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/28 ,  G06F1/08

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US20190235602A1

公开(公告)日：2019-08-01

申请号：US16379451

申请日：2019-04-09

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC: G06F1/3206 ,  H03K17/22 ,  G06F17/50 ,  H03K17/62

Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.

公开(公告)号：US11303268B2

公开(公告)日：2022-04-12

申请号：US17173055

申请日：2021-02-10

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC: H03K3/037 ,  H03K19/096 ,  H03K3/64

Abstract: A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.

公开(公告)号：US20220094340A1

公开(公告)日：2022-03-24

申请号：US17028790

申请日：2020-09-22

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Qi Ye

IPC: H03K3/037

Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.

公开(公告)号：US20210344329A1

公开(公告)日：2021-11-04

申请号：US17327365

申请日：2021-05-21

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

IPC: H03K3/012 ,  H03K3/037

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

公开(公告)号：US20210250019A1

公开(公告)日：2021-08-12

申请号：US17245623

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  H03K3/356 ,  G11C19/18

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

公开(公告)号：US11005459B1

公开(公告)日：2021-05-11

申请号：US16391085

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  G11C19/18 ,  H03K3/356

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.