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公开(公告)号：US09374103B1
公开(公告)日：2016-06-21
申请号：US14656052
申请日：2015-03-12
Applicant: Apple Inc.
Inventor： Wenbo Liu , Raman S. Thiara
CPC classification number: H03K17/165 , H03M1/687 , H03M1/76
Abstract: In some embodiments, a digital-to-analog converter (DAC) system includes an output segment, a main branch, first and second edge segments, and a sub-segment. The output segment includes secondary switches that selectively connect conductive paths to an output. The main branch includes unit resistance elements, each including a resistor and a switch. The first and second edge segments each include a respective group of secondary switches that selectively connect a respective conductive path to a unit resistance element. The sub-segment includes terminal resistors connected to at least one conductive path and includes main switches that selectively connect respective terminal resistors to the unit resistance element. The main switches and the unit resistance element switches use a single switch design. The DAC system may have an improved differential non-linearity (DNL), as compared to a DAC system that does not include the unit resistance element switches or the first and second edge segments.
Abstract translation: 在一些实施例中，数模转换器（DAC）系统包括输出段，主分支，第一和第二边缘段以及子段。 输出段包括将导电路径选择性地连接到输出的次级开关。 主分支包括单元电阻元件，每个元件包括电阻器和开关。 第一和第二边缘段各自包括相应的一组次级开关，其将相应的导电路径选择性地连接到单位电阻元件。 子段包括连接到至少一个导电路径的端子电阻器，并且包括主开关，其将各个端子电阻器选择性地连接到单位电阻元件。 主开关和单元电阻元件开关采用单开关设计。 与不包括单位电阻元件开关或第一和第二边缘段的DAC系统相比，DAC系统可具有改进的差分非线性（DNL）。
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公开(公告)号：US20210226639A1
公开(公告)日：2021-07-22
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US10972107B2
公开(公告)日：2021-04-06
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20210036707A1
公开(公告)日：2021-02-04
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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