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Patent Agency Ranking
公开(公告)号：US11770274B1
公开(公告)日：2023-09-26
申请号：US17664747
申请日：2022-05-24
Applicant: Apple Inc.
Inventor： Wing Liu , Sanjeev K. Maheshwari
IPC: H04L25/03
CPC classification number: H04L25/03057
Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.
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公开(公告)号：US11664809B2
公开(公告)日：2023-05-30
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
CPC classification number: H03L7/0818 , H03L7/0807 , H03L2207/12
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20210226639A1
公开(公告)日：2021-07-22
申请号：US17222667
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US10972107B2
公开(公告)日：2021-04-06
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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公开(公告)号：US20210036707A1
公开(公告)日：2021-02-04
申请号：US16528518
申请日：2019-07-31
Applicant: Apple Inc.
Inventor： Jaeduk Han , Wenbo Liu , Wing Liu , Ming-Shuan Chen , Sanjeev K. Maheshwari , Vishal Varma , Sunil Bhosekar , Lizhi Zhong , Gary A. Rogan
Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.
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