公开(公告)号：US11664809B2

公开(公告)日：2023-05-30

申请号：US17222667

申请日：2021-04-05

Applicant: Apple Inc.

Inventor： Jaeduk Han ,  Wenbo Liu ,  Wing Liu ,  Ming-Shuan Chen ,  Sanjeev K. Maheshwari ,  Vishal Varma ,  Sunil Bhosekar ,  Lizhi Zhong ,  Gary A. Rogan

IPC: H03L7/08 ,  H03L7/081

CPC classification number: H03L7/0818 ,  H03L7/0807 ,  H03L2207/12

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

公开(公告)号：US20220077679A1

公开(公告)日：2022-03-10

申请号：US17014894

申请日：2020-09-08

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Jaeduk Han ,  Praveen R. Singh

IPC: H02H9/04

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.

公开(公告)号：US11322935B2

公开(公告)日：2022-05-03

申请号：US17014894

申请日：2020-09-08

Applicant: Apple Inc.

Inventor： Farzan Farbiz ,  Jaeduk Han ,  Praveen R. Singh

IPC: H02H9/04

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.

公开(公告)号：US20210226639A1

公开(公告)日：2021-07-22

申请号：US17222667

申请日：2021-04-05

Applicant: Apple Inc.

Inventor： Jaeduk Han ,  Wenbo Liu ,  Wing Liu ,  Ming-Shuan Chen ,  Sanjeev K. Maheshwari ,  Vishal Varma ,  Sunil Bhosekar ,  Lizhi Zhong ,  Gary A. Rogan

IPC: H03L7/081 ,  H03L7/08

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

公开(公告)号：US10972107B2

公开(公告)日：2021-04-06

申请号：US16528518

申请日：2019-07-31

Applicant: Apple Inc.

Inventor： Jaeduk Han ,  Wenbo Liu ,  Wing Liu ,  Ming-Shuan Chen ,  Sanjeev K. Maheshwari ,  Vishal Varma ,  Sunil Bhosekar ,  Lizhi Zhong ,  Gary A. Rogan

IPC: H03L7/08 ,  H03L7/081

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

公开(公告)号：US20210036707A1

公开(公告)日：2021-02-04

申请号：US16528518

申请日：2019-07-31

Applicant: Apple Inc.

Inventor： Jaeduk Han ,  Wenbo Liu ,  Wing Liu ,  Ming-Shuan Chen ,  Sanjeev K. Maheshwari ,  Vishal Varma ,  Sunil Bhosekar ,  Lizhi Zhong ,  Gary A. Rogan

IPC: H03L7/081 ,  H03L7/08

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.