公开(公告)号：US06859387B1

公开(公告)日：2005-02-22

申请号：US09569954

申请日：2000-05-12

申请人： Arlo J. Aude ,  Laurence D. Lewicki

发明人： Arlo J. Aude ,  Laurence D. Lewicki

IPC分类号： G06F7/48 ,  H03M1/06 ,  H03M1/12 ,  H03M1/38 ,  H03M1/44

CPC分类号： G06F7/4824 ,  H03M1/0695 ,  H03M1/44

摘要： Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.”

摘要翻译： 公开了用于流水线模数转换器的三态二进制加法器。 根据一个有利的实施例，提供一种用于数字信号处理系统中的三态二进制加法器。 三态二进制加法器可操作以产生由三个状态组成的二进制码，即“00”，“01”和“10”。

公开(公告)号：US06469652B1

公开(公告)日：2002-10-22

申请号：US09645972

申请日：2000-08-24

申请人： Arlo J. Aude

发明人： Arlo J. Aude

IPC分类号： H03M144

CPC分类号： H03M1/0663 ,  H03M1/167 ,  H03M1/44

摘要： There is disclosed, for use in an analog to digital (ADC) converter, an ADC stage that receives a differential analog input signal, quantizes the differential analog input signal to a plurality of digital bits, and generates an output residue signal corresponding to a quantization error of the differential analog input signal. The ADC stage comprises: 1) a differential amplifier having an inverting input and a non-inverting input and a differential output comprising an inverting output and a non-inverting output; 2) a first capacitor having a first side and a second side and a second capacitor having a first side and a second side, wherein the second side of the first capacitor is coupled to the second side of the second capacitor and to the inverting input of the differential amplifier; 3) a third capacitor having a first side and a second side and a fourth capacitor having a first side and a second side, wherein the second side of the third capacitor is coupled to the second side of the fourth capacitor and to the non-inverting input of the differential amplifier; 4) a switch matrix for coupling the first sides of the first, second, third and fourth capacitors to selected ones of the first sides of the first, second, third and fourth capacitors, to selected ones of the inverting and non-inverting outputs of the differential amplifiers, and to selected ones of a positive reference voltage and a negative reference voltage; and 5) a switch control logic circuit for detecting a zero reference level crossing, wherein a voltage level on a preceding non-inverting output of a preceding ADC stage transitions from below a voltage level on a preceding inverting output of said preceding ADC stage to a voltage level above said voltage level on said preceding inverting output.

摘要翻译： 公开了用于模数（ADC）转换器的ADC级，其接收差分模拟输入信号，将差分模拟输入信号量化到多个数字位，并产生对应于量化的输出残留信号 差分模拟输入信号的误差。 ADC级包括：1）具有反相输入和非反相输入的差分放大器和包括反相输出和非反相输出的差分输出; 2）具有第一侧和第二侧的第一电容器和具有第一侧和第二侧的第二电容器，其中第一电容器的第二侧耦合到第二电容器的第二侧和第二电容器的反相输入端 差分放大器; 3）具有第一侧和第二侧的第三电容器和具有第一侧和第二侧的第四电容器，其中第三电容器的第二侧耦合到第四电容器的第二侧并且与非反相 输入差分放大器; 4）用于将第一，第二，第三和第四电容器的第一侧耦合到第一，第二，第三和第四电容器的第一侧中的选定的电容器的开关矩阵，以选择一个反相和非反相输出 差分放大器，以及正参考电压和负参考电压中的选择的差分放大器; 以及5）用于检测零参考电平交叉的开关控制逻辑电路，其中先前ADC级的前一个非反相输出端上的电压电平从所述先前ADC级的先前反相输出上的电压电平转换到 电压电平高于所述前一反相输出上的所述电压电平。