公开(公告)号：US06469652B1

公开(公告)日：2002-10-22

申请号：US09645972

申请日：2000-08-24

申请人： Arlo J. Aude

发明人： Arlo J. Aude

IPC分类号： H03M144

CPC分类号： H03M1/0663 ,  H03M1/167 ,  H03M1/44

摘要： There is disclosed, for use in an analog to digital (ADC) converter, an ADC stage that receives a differential analog input signal, quantizes the differential analog input signal to a plurality of digital bits, and generates an output residue signal corresponding to a quantization error of the differential analog input signal. The ADC stage comprises: 1) a differential amplifier having an inverting input and a non-inverting input and a differential output comprising an inverting output and a non-inverting output; 2) a first capacitor having a first side and a second side and a second capacitor having a first side and a second side, wherein the second side of the first capacitor is coupled to the second side of the second capacitor and to the inverting input of the differential amplifier; 3) a third capacitor having a first side and a second side and a fourth capacitor having a first side and a second side, wherein the second side of the third capacitor is coupled to the second side of the fourth capacitor and to the non-inverting input of the differential amplifier; 4) a switch matrix for coupling the first sides of the first, second, third and fourth capacitors to selected ones of the first sides of the first, second, third and fourth capacitors, to selected ones of the inverting and non-inverting outputs of the differential amplifiers, and to selected ones of a positive reference voltage and a negative reference voltage; and 5) a switch control logic circuit for detecting a zero reference level crossing, wherein a voltage level on a preceding non-inverting output of a preceding ADC stage transitions from below a voltage level on a preceding inverting output of said preceding ADC stage to a voltage level above said voltage level on said preceding inverting output.

摘要翻译： 公开了用于模数（ADC）转换器的ADC级，其接收差分模拟输入信号，将差分模拟输入信号量化到多个数字位，并产生对应于量化的输出残留信号 差分模拟输入信号的误差。 ADC级包括：1）具有反相输入和非反相输入的差分放大器和包括反相输出和非反相输出的差分输出; 2）具有第一侧和第二侧的第一电容器和具有第一侧和第二侧的第二电容器，其中第一电容器的第二侧耦合到第二电容器的第二侧和第二电容器的反相输入端 差分放大器; 3）具有第一侧和第二侧的第三电容器和具有第一侧和第二侧的第四电容器，其中第三电容器的第二侧耦合到第四电容器的第二侧并且与非反相 输入差分放大器; 4）用于将第一，第二，第三和第四电容器的第一侧耦合到第一，第二，第三和第四电容器的第一侧中的选定的电容器的开关矩阵，以选择一个反相和非反相输出 差分放大器，以及正参考电压和负参考电压中的选择的差分放大器; 以及5）用于检测零参考电平交叉的开关控制逻辑电路，其中先前ADC级的前一个非反相输出端上的电压电平从所述先前ADC级的先前反相输出上的电压电平转换到 电压电平高于所述前一反相输出上的所述电压电平。

公开(公告)号：US06462695B1

公开(公告)日：2002-10-08

申请号：US09945375

申请日：2001-08-31

申请人： Bhupendra Kumar Ahuja ,  Eric Glen Hoffman

发明人： Bhupendra Kumar Ahuja ,  Eric Glen Hoffman

IPC分类号： H03M144

CPC分类号： H03F3/45192 ,  H03F3/3023 ,  H03F2200/331 ,  H03M1/002 ,  H03M1/44

摘要： A method and circuitry for implementing low-power analog-to-digital converters. More particularly, embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages, some in sample mode, some in hold mode. The stages include residue amplifiers which include a pre-amp and a current source. The current source is turned off during the sample mode. Some embodiments include a second current source that provides a bleeder current during the sample phase so that the pre-amp remains in steady state.

摘要翻译： 一种用于实现低功耗模数转换器的方法和电路。 更具体地，本发明的实施例提供了一种用于具有多级的流水线ADC的放大器电路，一些在采样模式中，一些处于保持模式。 这些级包括残余放大器，其包括前置放大器和电流源。 在采样模式下，电流源关闭。 一些实施例包括在采样阶段期间提供泄流电流的第二电流源，使得前置放大器保持在稳定状态。

公开(公告)号：US06340944B1

公开(公告)日：2002-01-22

申请号：US09643385

申请日：2000-08-21

申请人： Ronald Chang ,  Jose A. Salcedo ,  Raphael Horton

发明人： Ronald Chang ,  Jose A. Salcedo ,  Raphael Horton

IPC分类号： H03M144

CPC分类号： H03M1/002 ,  H03M1/168 ,  H03M1/44

摘要： An analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs. In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably powered down, but not completely. By maintaining a small amount of bias current to the bypassed stages, they can quickly respond when a switch is made back to full resolution mode.

摘要翻译： 具有低分辨率和高分辨率模式的模数转换器。 响应于低分辨率模式信号，开关电路仅选择某些数字位输出。 在一个实施例中，模数转换器是具有多个级的流水线电路。 响应于低分辨率模式，旁路了多个级，使得仅使用较少位数的所需级。 被绕过的级优选地被断电，但不是完全。 通过保持少量的偏置电流到旁路级，当开关回到全分辨率模式时，它们可以快速响应。

公开(公告)号：US06664912B1

公开(公告)日：2003-12-16

申请号：US10243593

申请日：2002-09-13

申请人： Alfio Zanchi

发明人： Alfio Zanchi

IPC分类号： H03M144

CPC分类号： H03F3/45183 ,  H03F3/45188 ,  H03F3/45282 ,  H03F3/45286 ,  H03F3/4565 ,  H03F2203/45418 ,  H03F2203/45471 ,  H03F2203/45654

摘要： A preamplifier that is substantially resilient to temperature and input common-mode variations includes a feedback network coupled to regulate a common mode voltage of the preamplifier. The preamplifier can be implemented as a first stage of a multi-stage op amp, which provides an intermediate output to a next stage of the op amp. The feedback and associated temperature stability can be facilitated by downshifting the output voltage of the preamplifier and increasing the output impedance of the preamplifier.

摘要翻译： 基本上对温度和输入共模变化有弹性的前置放大器包括耦合以调节前置放大器的共模电压的反馈网络。 前置放大器可以实现为多级运算放大器的第一级，其向运算放大器的下一级提供中间输出。 通过降低前置放大器的输出电压并增加前置放大器的输出阻抗，可以有助于反馈和相关的温度稳定性。

公开(公告)号：US06556164B2

公开(公告)日：2003-04-29

申请号：US10209385

申请日：2002-07-29

申请人： Harald Schmid

发明人： Harald Schmid

IPC分类号： H03M144

CPC分类号： H03M1/462

摘要： An analog-to-digital converter for successively and approximately converting an analog input signal into a digital output signal includes at least one comparator having a linear input module and an output module. The analog input signal is compared with a compare signal supplied by a digital-to-analog converter and supplies a comparator output signal for adjusting a clocked successive approximation register. The digital value temporarily stored in the successive approximation register is converted into the analog compare signal by the digital-to-analog converter. The inventive converter also includes an acceleration circuit supplying a reversible clock signal to the cocked successive approximation register according to at least one overload detector signal that detects overload of an appurtenant linear input module in the comparator.

摘要翻译： 用于将模拟输入信号连续地和近似地转换为数字输出信号的模数转换器包括具有线性输入模块和输出模块的至少一个比较器。 将模拟输入信号与由数模转换器提供的比较信号进行比较，并提供比较器输出信号以调整时钟逐次逼近寄存器。 临时存储在逐次逼近寄存器中的数字值由数模转换器转换为模拟比较信号。 本发明的转换器还包括加速电路，该加速电路根据检测比较器中的附加线性输入模块的过载的至少一个过载检测器信号向可锁定的逐次逼近寄存器提供可逆时钟信号。

公开(公告)号：US06195032B1

公开(公告)日：2001-02-27

申请号：US09373472

申请日：1999-08-12

申请人： Minh V. Watson ,  Hessam Mohajeri

发明人： Minh V. Watson ,  Hessam Mohajeri

IPC分类号： H03M144

CPC分类号： H03M1/164 ,  H03M1/162 ,  H03M1/167 ,  H03M1/44

摘要： An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2B to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage. During successive clock periods, the first sub-stage converts B digital bits during a PH1 phase while the last sub-stage converts another B digital bits of less significance during the PH2 phase. The analog output from the last sub-stage is recycled back to the first sub-stage for the next clock and another 2B bits are converted in the next clock period. Once all of the MSB's have been converted, the last sub-stage outputs an analog residue voltage to the first sub-stage of the second pipeline stage, which then converts the LSB bits over several clock cycles using the same recycling method.

摘要翻译： 模数转换器（ADC）包含两个在两个不同模拟采样上并行运行的流水线级。 每个流水线阶段包括两个子阶段。 每个子级具有低分辨率ADC元件和低分辨率DAC元件。 ADC元件将模拟电压输入到子级转换为B数字位，其中B为低数字，如1，1.5或2.这些数字位由DAC元件重新转换回模拟DAC电压 。 减法器然后从子级的模拟输入电压中减去模拟DAC电压，以产生表示ADC / DAC元件的量化误差的差分电压。 乘法放大器将差分电压乘以2B，以产生到下一个子级的输出电压。 每个高级流水线级作为回收ADC，具有将最后一级的输出与第一级的模拟输入连接的反馈开关。 在连续时钟周期期间，第一子级在PH1阶段期间转换B数字位，而最后一级在PH2期间转换较低有效值的另一个B数字位。 来自最后一个子级的模拟输出被再循环回下一个时钟的第一个子级，另一个2B位在下一个时钟周期被转换。 一旦所有MSB都被转换，最后一个子级将模拟残留电压输出到第二流水线级的第一个子级，然后使用相同的回收方法在几个时钟周期内转换LSB位。