WIDE INPUT RANGE AND LOW NOISE COMPARATOR WITH TRIGGER TIMING CONTROL AND/OR GAIN BOOSTING

    公开(公告)号:US20240235571A9

    公开(公告)日:2024-07-11

    申请号:US18369816

    申请日:2023-09-18

    申请人: MEDIATEK INC.

    发明人: Wenchang Huang

    IPC分类号: H03M1/44 H03M1/18 H03M1/50

    CPC分类号: H03M1/44 H03M1/181 H03M1/502

    摘要: A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.

    WIDE INPUT RANGE AND LOW NOISE COMPARATOR WITH TRIGGER TIMING CONTROL AND/OR GAIN BOOSTING

    公开(公告)号:US20240137039A1

    公开(公告)日:2024-04-25

    申请号:US18369816

    申请日:2023-09-17

    申请人: MEDIATEK INC.

    发明人: Wenchang Huang

    IPC分类号: H03M1/44 H03M1/18 H03M1/50

    CPC分类号: H03M1/44 H03M1/181 H03M1/502

    摘要: A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.

    Inbuilt threshold comparator
    4.
    发明授权

    公开(公告)号:US09917594B1

    公开(公告)日:2018-03-13

    申请号:US15466691

    申请日:2017-03-22

    摘要: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.

    Continuous-time oversampling pipeline analog-to-digital converter
    7.
    发明授权
    Continuous-time oversampling pipeline analog-to-digital converter 有权
    连续时间过采样管线模数转换器

    公开(公告)号:US09432045B2

    公开(公告)日:2016-08-30

    申请号:US14524729

    申请日:2014-10-27

    发明人: Hajime Shibata

    摘要: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

    摘要翻译: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号,并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器,产生重构信号的解码器,产生延迟信号的延迟转换器和产生残差信号的放大器,其中延迟信号可以是连续电流信号。

    HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER
    8.
    发明申请
    HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER 有权
    用于模拟数字转换器的高速比较器

    公开(公告)号:US20160065229A1

    公开(公告)日:2016-03-03

    申请号:US14834871

    申请日:2015-08-25

    IPC分类号: H03M1/00 H03M1/12 H03M1/44

    摘要: A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit (30) to inject equal charges into the integration nodes.

    摘要翻译: 提供了一种用于模数转换器的比较器。 比较器包括差分放大器单元,其基于采样信号提供的电压接收采样信号并提供输出信号。 差分放大器单元包括输入级,其接收采样信号并且基于采样信号的电位对集成节点上的电流进行积分。 比较器包括与集成节点耦合的读出放大器,其检测电位差并放大电位差以产生输出信号。 该比较器包括一个电荷注入电路(30),用于向集成节点注入相等的电荷。

    Analog-to-digital converter with controlled error calibration
    9.
    发明授权
    Analog-to-digital converter with controlled error calibration 有权
    具有受控误差校准的模数转换器

    公开(公告)号:US09191021B1

    公开(公告)日:2015-11-17

    申请号:US14696482

    申请日:2015-04-26

    摘要: A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vin into a digital output value Dout. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vin and provides an ADC sub-module digital output value based on Vin, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal VDAC, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vin and VDAC, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

    摘要翻译: 用于将模拟输入电压信号Vin转换为数字输出值Dout的流水线模数转换器(ADC)。 ADC具有一系列级,包括第一校准级,其具有:(1)ADC子模块,其接收Vin并基于Vin提供ADC子模块数字输出值,(2)DAC子模块,其接收 ADC子模块数字输出值,并输出相应的模拟电压信号VDAC,(3)基于Vin和VDAC之间的差产生模拟残留电压信号的第一差分模块,(4)人造噪声插入 模块,其将模拟人造噪声电压信号插入残余电压信号中以产生模拟组合电压信号。 模拟组合电压信号用于校准第一个校准级。 人造噪声插入模块基于相应的残留电压信号的极性产生人为噪声电压信号的极性。

    Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm
    10.
    发明授权
    Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm 有权
    具有动态搜索算法的逐次逼近模数转换器(ADC)

    公开(公告)号:US09124294B2

    公开(公告)日:2015-09-01

    申请号:US14558004

    申请日:2014-12-02

    申请人: MaxLinear, Inc.

    摘要: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

    摘要翻译: 提供了具有动态搜索算法的逐次逼近模数转换器的方法和系统的方面。 在一些实施例中,逐次逼近模数转换器包括数模转换器,比较器以及搜索和解码逻辑模块,其协作以基于动态的方式产生代表模拟输入电压的数字输出代码 搜索算法。 动态搜索算法可以基于模拟输入电压的一个或多个特性改变用于连续逼近模拟输入电压的参考电压序列。