公开(公告)号：US20220300430A1

公开(公告)日：2022-09-22

申请号：US17208130

申请日：2021-03-22

Applicant: Arm Limited

Inventor： ABHISHEK RAJA

IPC: G06F12/0888

Abstract: An apparatus has processing circuitry, load tracking circuitry and value prediction circuitry. In response to an actual value of first target data becoming available for a value-predicted load operation, it is determined whether the actual value matches the predicted value of the first target data determined by the value prediction circuitry, and whether the tracking information indicates that, for a given younger load operation issued before the actual value of the first target data was available, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the value-predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the value prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.

公开(公告)号：US20190188149A1

公开(公告)日：2019-06-20

申请号：US15848397

申请日：2017-12-20

Applicant: Arm Limited

Inventor： ABHISHEK RAJA ,  Michael FILIPPO

IPC: G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F15/78 ,  G06F12/0891

CPC classification number: G06F12/1036 ,  G06F12/0891 ,  G06F12/1063 ,  G06F12/109 ,  G06F15/7839

Abstract: An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages. At an appropriate point, the prefetch circuitry triggers the control circuitry to allocate, into a selected entry of the address translation cache, coalesced address translation data that is derived from the candidate coalesced address translation data. Such an approach has been found to provide a particularly efficient mechanism for creating coalesced address translation data for allocating into the address translation cache, without impacting the latency of the servicing of ongoing requests from the request source.

公开(公告)号：US20180239714A1

公开(公告)日：2018-08-23

申请号：US15437581

申请日：2017-02-21

Applicant: ARM Limited

Inventor： ABHISHEK RAJA ,  Michael FILIPPO

IPC: G06F12/1045 ,  G06F12/0864 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/6032 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/681

Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation. The address translation cache is organised as a plurality of portions, and in the non-skewed mode the allocation circuitry is arranged, when performing the allocation process, to permit the address translation data to be allocated to any of the plurality of portions. In contrast, when in the at least one skewed mode, the allocation circuitry is arranged to reserve at least one portion for allocation of address translation data associated with pages of a first page size and at least one other portion for allocation of address translation data associated with pages of a second page size different to the first page size.

公开(公告)号：US20180101480A1

公开(公告)日：2018-04-12

申请号：US15290039

申请日：2016-10-11

Applicant: ARM LIMITED

Inventor： ABHISHEK RAJA

IPC: G06F12/1009 ,  G06F12/0875 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria. Each descriptor comprises physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allows the plurality of descriptors to have different values for a first subset of attributes when determining that the attribute match criteria is met. When the predetermined criteria are met, coalesced address translation data is generated from the plurality of descriptors and that coalesced address translation data is then stored in the selected entry. Otherwise, if the predetermined criteria is not met, address translation data is merely generated from the descriptor identified using the virtual address, and that address translation data is then stored in the selected entry. Such an approach significantly increases the effective capacity and performance of the address translation cache.