公开(公告)号：US20190272233A1

公开(公告)日：2019-09-05

申请号：US15910122

申请日：2018-03-02

Applicant: Arm Limited

Inventor： Lucas GARCIA ,  Geoffray Matthieu LACOURBA ,  Natalya BONDARENKO ,  Nathanael PREMILLIEU

IPC: G06F12/0862

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses which resulted in a cache miss or an access to a previously prefetched data element, for which the memory address for that data element access differs by the candidate offset value from a memory address in the address table; in which the detector circuitry is configured to process the group of candidate offset values as successive complementary sub-groups of one or more of the group of candidate offset values and to set a next instance of the current offset value in response to processing each sub-group, in dependence upon the proportions indicated by the one or more detected metrics for that sub-group; and the one or more metrics previously detected for the current offset value.

公开(公告)号：US20240241723A1

公开(公告)日：2024-07-18

申请号：US18096141

申请日：2023-01-12

Applicant: Arm Limited

Inventor： Luca NASSI ,  Geoffray Matthieu LACOURBA ,  Cédric Denis Robert AIRAUD ,  Albin Pierrick TONNERRE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/30094 ,  G06F9/384

Abstract: A data processing apparatus is provided. Instruction send circuitry sends an instruction to an external processor to be executed by the external processor. Allocation circuitry allocates a specified one of several registers for a result of the instruction having been executed on the external processor and data receive circuitry receives the result of the instruction having been executed on the external processor and stores the result in the specified one of the several registers. In response to a condition being met: the specified one of the several registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.

公开(公告)号：US20220229783A1

公开(公告)日：2022-07-21

申请号：US17153147

申请日：2021-01-20

Applicant: Arm Limited

Inventor： Frederic Claude Marie PIRY ,  Natalya BONDARENKO ,  Cédric Denis Robert AIRAUD ,  Geoffray Matthieu LACOURBA

IPC: G06F12/126 ,  G06F12/02 ,  G06K9/62

Abstract: A technique is provided for training a prediction apparatus. The apparatus has an input interface for receiving a sequence of training events indicative of program instructions, and identifier value generation circuitry for performing an identifier value generation function to generate, for a given training event received at the input interface, an identifier value for that given training event. The identifier value generation function is arranged such that the generated identifier value is dependent on at least one register referenced by a program instruction indicated by that given training event. Prediction storage is provided with a plurality of training entries, where each training entry is allocated an identifier value as generated by the identifier value generation function, and is used to maintain training data derived from training events having that allocated identifier value. Matching circuitry is then responsive to the given training event to detect whether the prediction storage has a matching training entry (i.e. an entry whose allocated identifier value matches the identifier value for the given training event). If so, it causes the training data in the matching training entry to be updated in dependence on the given training event.

公开(公告)号：US20190272234A1

公开(公告)日：2019-09-05

申请号：US15910137

申请日：2018-03-02

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Lucas GARCIA ,  Geoffray Matthieu LACOURBA

IPC: G06F12/0862

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses which resulted in a cache miss or an access to a previously prefetched data element, for which the memory address for that data element access differs by the candidate offset value from a memory address in the address table; in which the detector circuitry is configured to set a next instance of the current offset value in response to the one or more detected metrics; verification circuitry to detect, at one or more predetermined stages with respect to the processing of the group of candidate offset values by the offset value selection circuitry, one or more verification metrics representing a proportion of a set of data element accesses which resulted in a cache miss or an access to a previously prefetched data element, for which the memory address for that data element access differs by the current offset value from a memory address in the address table, to detect whether the one or more verification metrics comply with a predetermined condition; and control circuitry to inhibit prefetching at least until a next selection of a current offset value by the offset value selection circuitry, in response to a detection by the verification circuitry that the one or more verification metrics do not comply with the predetermined condition.

公开(公告)号：US20180225214A1

公开(公告)日：2018-08-09

申请号：US15427459

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Michael FILIPPO ,  Paul Gilbert MEYER ,  Alex James WAUGH ,  Geoffray Matthieu LACOURBA

IPC: G06F12/0831 ,  G06F9/46

CPC classification number: G06F12/0835 ,  G06F12/0808 ,  G06F2212/1024 ,  G06F2212/621

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

公开(公告)号：US20140258622A1

公开(公告)日：2014-09-11

申请号：US13788538

申请日：2013-03-07

Applicant: ARM LIMITED

Inventor： Geoffray Matthieu LACOURBA ,  Philippe Jean-Pierre Raphalen

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0811 ,  G06F2212/6024 ,  G06F2212/6026 ,  Y02D10/13

Abstract: A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests.

Abstract translation: 数据处理装置包括处理器和分层数据存储系统，包括存储器和高速缓存，用于将数据和指令存储在由物理地址识别的存储位置中。 该设备包括用于将虚拟地址映射到物理地址的地址转换电路，以及从处理器接收访问请求的加载存储电路。 存储电路访问转换电路以识别对应于接收到的数据访问请求的虚拟地址的物理地址，并访问分层数据存储系统中的对应的物理地址。 预加载电路从处理器接收指示要预加载的虚拟地址存储位置的预加载请求。 预取电路监视由加载存储电路执行的至少一些访问，并预测随后要访问的地址，并将预测地址作为预加载请求发送到预加载电路。