公开(公告)号：US20250004767A1

公开(公告)日：2025-01-02

申请号：US18345164

申请日：2023-06-30

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Albin Pierrick TONNERRE ,  Geoffray Matthieu LACOURBA

IPC: G06F9/30

Abstract: Mode change detection circuitry detects a mode change when processing circuitry switches between first and second modes of processing in which a first set of architectural registers are designated as having different register lengths. Register mapping circuitry maps architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to a determination that the operation is to be processed in the first mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a first physical register file, and in response to a determination that the operation is to be processed in the second mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file separate from the first physical register file and having physical registers of different register length to physical registers of the first physical register file.

公开(公告)号：US20220308880A1

公开(公告)日：2022-09-29

申请号：US17209515

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Stefano GHIGGINI ,  Geoffray Matthieu LACOURBA ,  Cédric Denis Robert AIRAUD

IPC: G06F9/38 ,  G06N20/00

Abstract: The invention provides a data processing apparatus and a data processing method for generating prefetches of data for use during execution of instructions by processing circuitry. The prefetches that are generated are based on a nested prefetch pattern. The nested prefetch pattern comprises a first pattern and a second pattern. The first pattern is defined by a first address offset between sequentially accessed addresses and a first observed number of the sequentially accessed addresses separated by the first address offset. The second pattern is defined by a second address offset between sequential iterations of the first pattern and a second observed number of the sequential iterations of the first pattern separated by the second address offset.

公开(公告)号：US20240126458A1

公开(公告)日：2024-04-18

申请号：US17966071

申请日：2022-10-14

Applicant: Arm Limited

Inventor： Stefano GHIGGINI ,  Natalya Bondarenko ,  Luca NASSI ,  Geoffray Matthieu LACOURBA ,  Huzefa Moiz SANJELIWALA ,  Miles Robert DOOLEY ,  . ABHISHEK RAJA

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

公开(公告)号：US20180225047A1

公开(公告)日：2018-08-09

申请号：US15427335

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Klas Magnus BRUCE ,  Geoffray Matthieu LACOURBA

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0683 ,  G06F9/52 ,  G06F9/526 ,  G06F12/06 ,  G06F2212/1024

Abstract: A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

公开(公告)号：US20200327062A1

公开(公告)日：2020-10-15

申请号：US16382394

申请日：2019-04-12

Applicant: Arm Limited

Inventor： Geoffray Matthieu LACOURBA ,  Andrew John TURNER ,  Alex James WAUGH

IPC: G06F12/0868 ,  G06F13/38 ,  G06F13/14

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

公开(公告)号：US20200259756A1

公开(公告)日：2020-08-13

申请号：US16269740

申请日：2019-02-07

Applicant: Arm Limited

Inventor： Geoffray Matthieu LACOURBA ,  Alex James WAUGH

IPC: H04L12/801 ,  H04L12/933

Abstract: An interconnect is provided that has a plurality of nodes, and a ring network to which each of the nodes is connected to allow packets to be transmitted between nodes. For an ordered sequence of packets one of the nodes is arranged as a source node to add each packet of the ordered sequence on to the ring network, and another of the nodes is arranged as a destination node to remove each packet of the ordered sequence from the ring network. The source node is enabled to add a packet of the ordered sequence on to the ring network without waiting for a previously added packet of the ordered sequence to be removed from the ring network by the destination node. When the destination node is unable to accept a given packet of the ordered sequence that is currently being presented to the destination node by the ring network, that given packet remains on the ring network and continues to be transmitted around the ring network such that after a respin period that given packet will be presented again to the destination node. The destination node is then arranged to prevent acceptance of at least any other packets of the ordered sequence subsequently presented to the destination node by the ring network until the destination node has accepted the given packet following at least one respin period. This can improve the efficiency of the ring network in the handling of ordered sequences of packets, whilst still ensuring the ordering constraints are met.

公开(公告)号：US20200250094A1

公开(公告)日：2020-08-06

申请号：US16266185

申请日：2019-02-04

Applicant: Arm Limited

Inventor： Alex James WAUGH ,  Geoffray Matthieu LACOURBA

IPC: G06F12/0815 ,  H04L12/747 ,  G06F12/0811 ,  G06F12/0862

Abstract: An interconnect, and method of operation of such an interconnect, are disclosed. The interconnect has a plurality of nodes, and a routing network via which information is routed between the plurality of nodes. The plurality of nodes comprises at least one slave node used to couple master devices to the interconnect, at least one master node used to couple slave devices to the interconnect, and at least one control node. Each control node is responsive to a slave node request received via the routing network from a slave node, to perform an operation to service the slave node request and, when a propagation condition is present, to issue a control node request via the routing network to a chosen master node in order to service the slave node request. The chosen master node processes the control node request in order to generate a master node response, and treats as a default destination for the master node response the control node that issued the control node request. In response to a trigger event occurring after the control node request has been issued, the control node sends an update destination request to the chosen master node that identifies a replacement destination node for the master node response. At least in the absence of an override condition, the chosen master node then sends the master node response via the routing network to the replacement destination node.

公开(公告)号：US20250053421A1

公开(公告)日：2025-02-13

申请号：US18448240

申请日：2023-08-11

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Albin Pierrick TONNERRE ,  Geoffray Matthieu LACOURBA

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers and corresponding physical registers, and register rename circuitry to update the register mappings indicated by the rename entries. Rename entries corresponding to at least one set of architectural registers support a cleared-register encoding. In response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, the register rename circuitry controls the processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value. In response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, the register rename circuitry sets rename entries corresponding to the at least one set of architectural registers to the cleared-register encoding.

公开(公告)号：US20250004769A1

公开(公告)日：2025-01-02

申请号：US18343294

申请日：2023-06-28

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Nicola PIANO ,  Albin Pierrick TONNERRE ,  Geoffray Matthieu LACOURBA

IPC: G06F9/30

Abstract: There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.

公开(公告)号：US20230042247A1

公开(公告)日：2023-02-09

申请号：US17396865

申请日：2021-08-09

Applicant: Arm Limited

Inventor： Frederic Claude Marie PIRY ,  Cédric Denis Robert AIRAUD ,  Natalya BONDARENKO ,  Luca MARONCELLI ,  Geoffray Matthieu LACOURBA

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A data processing apparatus comprises receiver circuitry for receiving instructions from each of a plurality of requester devices. Processing circuitry executes the instructions associated with each of a subset of the requester devices at a time and arbitration circuitry determines the subset of the requester devices and causes the instructions associated with each of the subset of the requester devices to be executed next. In response to the receiver circuitry receiving an instruction of a predetermined type from one of the requester devices outside the subset of requester devices, the arbitration circuitry causes the instruction of the predetermined type to be executed next.