公开(公告)号：US10963253B2

公开(公告)日：2021-03-30

申请号：US16030963

申请日：2018-07-10

Applicant: Arm Limited

Inventor： Karel Hubertus Gerardus Walters ,  Chiloda Ashan Senarath Pathirane ,  Michael Alexander Kennedy

IPC: G06F15/00 ,  G06F9/30

Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.

公开(公告)号：US09330035B2

公开(公告)日：2016-05-03

申请号：US13900777

申请日：2013-05-23

Applicant: ARM LIMITED

Inventor： Anthony Jebson ,  Richard Roy Grisenthwaite ,  Michael Alexander Kennedy ,  Ian Michael Caulfield

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/4818

Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.

Abstract translation: 数据处理装置包括多个系统寄存器和一组用于控制进入中断的处理的中断处理寄存器。 所述设备还包括被配置为执行所述多个执行级别的软件的处理电路，以及被配置为将所述输入中断路由到中断处理软件的中断控制器电路，所述中断处理软件被配置为在所述多个执行级中的一个执行级别运行，并且将访问控制电路 配置为根据所述多个执行级别中的一个来动态地控制对至少一些所述中断处理寄存器的访问，所述多个执行级别中的所述进入中断被路由到。 配置为在特定执行级别运行的中断处理软件无法访问中断处理寄存器，用于处理被配置为以更特权的执行级运行的中断处理软件的不同输入中断。

公开(公告)号：US20150227477A1

公开(公告)日：2015-08-13

申请号：US14695325

申请日：2015-04-24

Applicant: ARM Limited

Inventor： Michael Alexander Kennedy ,  Anthony Jebson

IPC: G06F13/24 ,  G06F11/30

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

Abstract translation: 数据处理装置具有多个处理器和多个中断接口，每个中断接口用于处理来自相应处理器的中断请求。 中断分配器控制中断请求到中断接口的路由。 共享中断请求可由多个处理器使用。 响应于共享中断请求，目标中断接口向中断分配器发出中断所有权请求，如果它估计相应的处理器可用于维护共享中断请求，则不会将共享中断请求传递给相应的处理器。 当从中断分配器接收到所有权确认，指示处理器被选择用于维护共享中断请求时，共享中断请求被传递给相应的处理器。