公开(公告)号：US09378162B2

公开(公告)日：2016-06-28

申请号：US13898816

申请日：2013-05-21

Applicant: ARM LIMITED

Inventor： Anthony Jebson ,  Andrew John Turner ,  Matthew Lucien Evans ,  Gareth James Evans ,  Adam James McNeeney

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Abstract translation: 一种中断控制器，用于控制在包括至少一个物理处理单元的数据处理装置处接收的中断的路由和处理，所述物理处理单元被配置为运行多个虚拟处理器和存储器中的至少一个。 中断控制器包括具有与单元对应的至少一个数据存储器的再分配电路，数据存储器存储指向虚拟挂起表的指针，该虚拟挂起表存储当前在相应单元上运行的虚拟处理器的当前待处理的虚拟中断，以及指向待处理表的指针 被配置为存储用于相应单元的当前待处理的物理中断，以及被配置为接收用于中断虚拟处理器的虚拟中断的输入。 控制电路被配置为将虚拟中断添加到虚拟挂起表并将虚拟中断存储在存储在存储器中的虚拟处理器的虚拟挂起表中。

公开(公告)号：US09330035B2

公开(公告)日：2016-05-03

申请号：US13900777

申请日：2013-05-23

Applicant: ARM LIMITED

Inventor： Anthony Jebson ,  Richard Roy Grisenthwaite ,  Michael Alexander Kennedy ,  Ian Michael Caulfield

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/4818

Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.

Abstract translation: 数据处理装置包括多个系统寄存器和一组用于控制进入中断的处理的中断处理寄存器。 所述设备还包括被配置为执行所述多个执行级别的软件的处理电路，以及被配置为将所述输入中断路由到中断处理软件的中断控制器电路，所述中断处理软件被配置为在所述多个执行级中的一个执行级别运行，并且将访问控制电路 配置为根据所述多个执行级别中的一个来动态地控制对至少一些所述中断处理寄存器的访问，所述多个执行级别中的所述进入中断被路由到。 配置为在特定执行级别运行的中断处理软件无法访问中断处理寄存器，用于处理被配置为以更特权的执行级运行的中断处理软件的不同输入中断。

公开(公告)号：US20150227477A1

公开(公告)日：2015-08-13

申请号：US14695325

申请日：2015-04-24

Applicant: ARM Limited

Inventor： Michael Alexander Kennedy ,  Anthony Jebson

IPC: G06F13/24 ,  G06F11/30

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

Abstract translation: 数据处理装置具有多个处理器和多个中断接口，每个中断接口用于处理来自相应处理器的中断请求。 中断分配器控制中断请求到中断接口的路由。 共享中断请求可由多个处理器使用。 响应于共享中断请求，目标中断接口向中断分配器发出中断所有权请求，如果它估计相应的处理器可用于维护共享中断请求，则不会将共享中断请求传递给相应的处理器。 当从中断分配器接收到所有权确认，指示处理器被选择用于维护共享中断请求时，共享中断请求被传递给相应的处理器。

公开(公告)号：US10019394B2

公开(公告)日：2018-07-10

申请号：US15464892

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Michael Alexander Kennedy ,  Anthony Jebson

IPC: G06F13/24 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

公开(公告)号：US09632957B2

公开(公告)日：2017-04-25

申请号：US14695325

申请日：2015-04-24

Applicant: ARM Limited

Inventor： Michael Alexander Kennedy ,  Anthony Jebson

IPC: G06F13/24 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

公开(公告)号：US08924615B2

公开(公告)日：2014-12-30

申请号：US13661456

申请日：2012-10-26

Applicant: ARM Limited

Inventor： Richard Roy Grisenthwaite ,  Anthony Jebson ,  Andrew Christopher Rose ,  Matthew Lucien Evans

IPC: G06F13/26 ,  G06F13/24

CPC classification number: G06F13/26 ,  G06F13/24

Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract translation: 提供全局中断号码空间38用于消息信号中断。 中断目的地10,12,14,16提供有等待中断高速缓存24，其中由全局挂起状态存储器34提供的后备存储器由全部高速缓存或独立的各个未决状态存储器56共享。中断号码空间可以被划分为具有 可编程映射数据用于指示哪些中断目的地负责哪些区域。 当中断从一个中断目的地迁移到另一个中断时，这种可编程映射数据被更新。 在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

公开(公告)号：US09043522B2

公开(公告)日：2015-05-26

申请号：US13653472

申请日：2012-10-17

Applicant: ARM LIMITED

Inventor： Michael Alexander Kennedy ,  Anthony Jebson

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F9/5027

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

Abstract translation: 数据处理装置具有多个处理器和多个中断接口，每个中断接口用于处理来自相应处理器的中断请求。 中断分配器控制中断请求到中断接口的路由。 共享中断请求可由多个处理器使用。 响应于共享中断请求，目标中断接口向中断分配器发出中断所有权请求，如果它估计相应的处理器可用于维护共享中断请求，则不会将共享中断请求传递给相应的处理器。 当从中断分配器接收到所有权确认，指示处理器被选择用于维护共享中断请求时，共享中断请求被传递给相应的处理器。