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公开(公告)号：US20210295138A1
公开(公告)日：2021-09-23
申请号：US16823063
申请日：2020-03-18
Applicant: Arm Limited
Inventor： Dominic Hugo Symes , Rune Holm
Abstract: A method for performing neural network processing, and a corresponding data processing system. The data processing system is configured to define one or more tiles for use when reading a portion of an input feature map from memory or writing a portion of an output feature map to memory. The data processing system is also configured to provide information which allows positions falling within the defined one or more tiles to be mapped to memory locations to allow a processor to read data for an input feature map from memory or to write data for a portion of an output feature map to memory.
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公开(公告)号：US10528350B2
公开(公告)日：2020-01-07
申请号：US15505714
申请日：2015-07-28
Applicant: ARM LIMITED
Inventor： Rune Holm , David Hennah Mansell
Abstract: A data processing apparatus (100) executes threads and includes a general program counter (PC) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread PC (184). The subset of threads has at least one lock parameter (188, 500-504) for tracking exclusive access to shared resources. In response to a first instruction executed for a thread, the processor (160) modifies the at least one lock parameter (188), (500-504) to indicate that the thread has gained exclusive access to the shared resource. In response to a second instruction, the processor modifies the at least one lock parameter (188, 500-504) to indicate that the thread no longer has exclusive access. A selector (110) selects one of the subset of threads based on the at least one lock parameter (188, 500-504) and sets the general PC (120) to the thread PC (184) of the selected thread.
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公开(公告)号：US09037835B1
公开(公告)日：2015-05-19
申请号：US14061842
申请日：2013-10-24
Applicant: ARM LIMITED
Inventor： Ganesh Suryanarayan Dasika , Rune Holm
CPC classification number: G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F2212/6026
Abstract: A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.
Abstract translation: 数据处理设备包括处理电路20，用于执行对存储器件40的第一地址的第一存储器访问指令和到存储器件40的第二地址的第二存储器访问指令，第一地址不同于第二地址。 数据处理装置还包括预取电路30，用于基于步幅长度70和指令分析电路50从存储器装置40预取数据，用于确定第一地址和第二地址之间的差异。 还提供跨步精炼电路60以基于步幅长度的因素和由指令分析电路50计算的差异的因素来细化步幅长度。
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公开(公告)号：US12124935B2
公开(公告)日：2024-10-22
申请号：US16797210
申请日：2020-02-21
Applicant: Arm Limited
Inventor： Suraj Sudhir , Jayavarapu Srinivasa Rao , Rune Holm
Abstract: A computer-implemented method, performed in a neural processing system comprising control processor circuitry and arithmetic logic circuitry, of performing a convolution between an input feature map (IFM) and convolutional filter data, resulting in an output feature map (OFM). The method includes, obtaining in the control processor circuitry, dimensional characteristic parameters relating to dimensions of input work batch data arrays and positional characteristic parameters relating to positions of feature map content within the input work batches. The method also includes, in the arithmetic logic circuitry, performing convolutions between the input work batches, generated from the IFM based on the dimensional characteristic parameters and the positional characteristic parameters, and work batch filter data arrays corresponding to the filter to produce a plurality of output work batch data arrays. The plurality of output work batches are combined to generate an OFM.
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公开(公告)号：US12032506B2
公开(公告)日：2024-07-09
申请号：US17709280
申请日：2022-03-30
Applicant: Arm Limited
Inventor： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC: H04L49/101 , G06F13/42 , G06N5/04
Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.
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Patent Agency Ranking
公开(公告)号：US11874793B2
公开(公告)日：2024-01-16
申请号：US17709255
申请日：2022-03-30
Applicant: Arm Limited
Inventor： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
IPC: G06F15/80
CPC classification number: G06F15/80
Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast hubs for multi-processor arrangements. A processing tile may comprise a broadcast hub to obtain a plurality of parameters applicable in a particular operation from at least one of a plurality of processing tiles and initiate distribution of the plurality of parameters to the plurality of processing tiles, wherein the plurality of processing tiles may execute the particular operation based at least in part on the plurality of distributed parameters.
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公开(公告)号：US11842273B2
公开(公告)日：2023-12-12
申请号：US17030176
申请日：2020-09-23
Applicant: Arm Limited
Abstract: To perform neural network processing to modify an input data array to generate a corresponding output data array using a filter comprising an array of weight data, at least one of the input data array and the filter are subdivided into a plurality of portions, a plurality of neural network processing passes using the portions are performed, and the output generated by each processing pass is combined to provide the output data array.
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公开(公告)号：US20230315669A1
公开(公告)日：2023-10-05
申请号：US17709280
申请日：2022-03-30
Applicant: Arm Limited
Inventor： Erik Persson , Graeme Leslie Ingram , Rune Holm , John Wakefield Brothers, III
Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.
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公开(公告)号：US11741349B2
公开(公告)日：2023-08-29
申请号：US16670140
申请日：2019-10-31
Applicant: Arm Limited
Inventor： Rune Holm , John Wakefield Brothers, III
CPC classification number: G06N3/063 , G06F7/5443 , G06F17/16 , G06N3/044
Abstract: When performing a matrix-vector multiply operation for neural network processing, a set of one or more input vectors to be multiplied by a matrix of data values is scanned to identify data positions of the input vector(s) for which the data value is non-zero in at least one of the input vectors. For each of the data positions identified as having a non-zero value in at least one of the input vectors, the set of data values from the matrix of data values for that data position is fetched from memory and the matrix-vector multiply operation is performed using the data values for the input vectors for the data positions identified as being non-zero and the fetched set(s) of data values from the matrix of data values for those data position(s).
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公开(公告)号：US11620503B2
公开(公告)日：2023-04-04
申请号：US16823063
申请日：2020-03-18
Applicant: Arm Limited
Inventor： Dominic Hugo Symes , Rune Holm
Abstract: A method for performing neural network processing, and a corresponding data processing system. The data processing system is configured to define one or more tiles for use when reading a portion of an input feature map from memory or writing a portion of an output feature map to memory. The data processing system is also configured to provide information which allows positions falling within the defined one or more tiles to be mapped to memory locations to allow a processor to read data for an input feature map from memory or to write data for a portion of an output feature map to memory.
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