公开(公告)号：US20230315677A1

公开(公告)日：2023-10-05

申请号：US17709255

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F15/80

CPC classification number: G06F15/80

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast hubs for multi-processor arrangements. A processing tile may comprise a broadcast hub to obtain a plurality of parameters applicable in a particular operation from at least one of a plurality of processing tiles and initiate distribution of the plurality of parameters to the plurality of processing tiles, wherein the plurality of processing tiles may execute the particular operation based at least in part on the plurality of distributed parameters.

公开(公告)号：US12001369B2

公开(公告)日：2024-06-04

申请号：US17709293

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

公开(公告)号：US20230315670A1

公开(公告)日：2023-10-05

申请号：US17709293

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

公开(公告)号：US12032506B2

公开(公告)日：2024-07-09

申请号：US17709280

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: H04L49/101 ,  G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.

公开(公告)号：US11874793B2

公开(公告)日：2024-01-16

申请号：US17709255

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F15/80

CPC classification number: G06F15/80

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast hubs for multi-processor arrangements. A processing tile may comprise a broadcast hub to obtain a plurality of parameters applicable in a particular operation from at least one of a plurality of processing tiles and initiate distribution of the plurality of parameters to the plurality of processing tiles, wherein the plurality of processing tiles may execute the particular operation based at least in part on the plurality of distributed parameters.

公开(公告)号：US20230315669A1

公开(公告)日：2023-10-05

申请号：US17709280

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Erik Persson ,  Graeme Leslie Ingram ,  Rune Holm ,  John Wakefield Brothers, III

IPC: G06F13/42 ,  G06N5/04

CPC classification number: G06F13/42 ,  G06N5/04

Abstract: The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.

公开(公告)号：US11599391B2

公开(公告)日：2023-03-07

申请号：US16592074

申请日：2019-10-03

Applicant: Arm Limited

Inventor： Graeme Leslie Ingram

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/54 ,  G06F3/06 ,  G06F13/16

Abstract: A method of requesting data items from storage. The method comprising allocating each of a plurality of memory controllers a unique identifier and assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers. The data items are spatially local to one another in storage. The data items are requested from the storage via the memory controllers according to the memory transaction requests and then buffered if the data items are received out of order relative to an order in which the data items are requested.

公开(公告)号：US10977184B2

公开(公告)日：2021-04-13

申请号：US16447728

申请日：2019-06-20

Applicant: Apical Limited ,  Arm Limited

Inventor： Sharjeel Saeed ,  Daren Croxford ,  Graeme Leslie Ingram

IPC: G06F12/00 ,  G06F12/10 ,  G06N3/04

Abstract: A method for managing memory access for implementing at least one layer of a convolutional neural network is provided. The method comprises predicting an access procedure in relation to a portion of memory based on a characteristic of the convolutional neural network. In response to the prediction, the method comprises performing an operation to obtain and store a memory address translation, corresponding to the portion of memory, in storage in advance of the predicted access procedure. An apparatus is provided comprising at least one processor and storage. The apparatus is configured to predict an access procedure in relation to a portion of memory which is external to the processor. In response to the prediction, the apparatus is configured to obtain and store a memory address translation corresponding to the portion of memory in storage in advance of the predicted access procedure.

公开(公告)号：US12174743B2

公开(公告)日：2024-12-24

申请号：US17643732

申请日：2021-12-10

Applicant: Arm Limited

Inventor： Graeme Leslie Ingram ,  Michael Jean Sole ,  Erik Persson

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1081 ,  G06N3/02

Abstract: A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

公开(公告)号：US11797454B2

公开(公告)日：2023-10-24

申请号：US17532555

申请日：2021-11-22

Applicant: Arm Limited

Inventor： Graeme Leslie Ingram ,  Michael Andrew Campbell

IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/0877

CPC classification number: G06F12/0871 ,  G06F12/0246 ,  G06F12/0808 ,  G06F12/0877

Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.