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    Minimal headroom, minimal area multi-terminal current steering circuits
    15.
    发明授权
    Minimal headroom, minimal area multi-terminal current steering circuits 失效
    最小的余量，最小面积的多端子电流转向电路

    公开(公告)号：US6014045A

    公开(公告)日：2000-01-11

    申请号：US89651

    申请日：1998-06-03

    Applicant: Arya R. Behzad

    Inventor： Arya R. Behzad

    IPC: H03K17/00 ,  H03K17/041 ,  H03K17/62 ,  H03K5/153

    CPC classification number: H03K17/04113 ,  H03K17/6292 ,  H03K2217/0036

    Abstract: Minimal headroom, minimal area, multi-terminal current steering circuits for steering a current from a current source to any one of a plurality of outputs. The steering circuit provides controls to individual steering transistors so as to turn on the selected one of the plurality of steering transistors responsive to steering control signals. Minimal headroom is required, and beta dependent errors in the current output are minimized, by steering the current source through only a single transistor to the selected output. This also minimizes chip area. Alternate embodiments are disclosed and described.

    Abstract translation: 最小余量，最小面积，用于将来自电流源的电流转向多个输出中的任何一个的多端子电流转向电路。 转向电路为单独的转向晶体管提供控制，以响应于转向控制信号来接通多个转向晶体管中所选择的一个。 需要最小的净空，并通过将电流源通过仅一个晶体管转向所选输出来将电流输出中的β相关误差最小化。 这也使芯片面积最小化。 公开和描述了替代实施例。

    Large gain range, high linearity, low noise MOS VGA
    20.
    发明授权
    Large gain range, high linearity, low noise MOS VGA 有权
    大增益范围，高线性度，低噪声MOS VGA

    公开(公告)号：US06759904B2

    公开(公告)日：2004-07-06

    申请号：US10183552

    申请日：2002-06-28

    Applicant: Arya R. Behzad

    Inventor： Arya R. Behzad

    IPC: H03F345

    CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

    Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

    Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.频率规划提供额外的图像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合差分对放大器实现的失真消除，其具有与差分对源的电流转向结合动态修改的Vds。

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