公开(公告)号：US20230421425A1

公开(公告)日：2023-12-28

申请号：US17847896

申请日：2022-06-23

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Christopher N. Peters ,  David D. Moser

IPC: H04L27/26 ,  G06F17/14

CPC classification number: H04L27/2651 ,  G06F17/142

Abstract: Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.

公开(公告)号：US20230421137A1

公开(公告)日：2023-12-28

申请号：US17847892

申请日：2022-06-23

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Christopher N. Peters ,  David D. Moser

IPC: H03H17/02 ,  G06F7/50 ,  G06F7/523

CPC classification number: H03H17/0227 ,  G06F7/523 ,  G06F7/50

Abstract: Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.

公开(公告)号：US20230418898A1

公开(公告)日：2023-12-28

申请号：US17847887

申请日：2022-06-23

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Christopher N. Peters ,  David D. Moser

IPC: G06F17/14 ,  H04B1/18 ,  H04L25/03 ,  H03H17/02

CPC classification number: G06F17/142 ,  H04B1/18 ,  H04L25/03828 ,  H03H17/0223

Abstract: Techniques are provided for a dynamically reconfigurable two times (2×) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2× oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2× oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.

公开(公告)号：US20230366931A1

公开(公告)日：2023-11-16

申请号：US17742034

申请日：2022-05-11

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Daniel L. Stanley ,  David D. Moser ,  Joshua C. Schabel ,  Michael J. Bear ,  Sheldon L. Grass ,  Tate J. Keegan

IPC: G01R31/3185

CPC classification number: G01R31/318597

Abstract: A port protection network provided with a joint test action group (JTAG) core and method of use. The port protection network includes an agent device operatively connected with a streaming bus and a test access port (TAP) of the JTAG core. The port protection network also includes a master device operatively connected with the streaming bus and the TAP of the JTAG core. In the port protection network, the agent device is configured to selectively restrict access to the master device through the JTAG core.

公开(公告)号：US10990727B1

公开(公告)日：2021-04-27

申请号：US17016816

申请日：2020-09-10

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Brian A. Saari ,  Stephen A. Chadwick ,  Jason T. Dowling ,  Michael J. Frack ,  David D. Moser ,  Mark R. Shaffer

IPC: G06F30/33 ,  G06F30/343 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/398 ,  G06F30/333

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.