公开(公告)号：US20220278687A1

公开(公告)日：2022-09-01

申请号：US17689605

申请日：2022-03-08

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Steven E. Turner ,  Joseph D. Cali

IPC: H03L7/093 ,  H03M3/00 ,  G06F1/02

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

公开(公告)号：US11012079B1

公开(公告)日：2021-05-18

申请号：US16721494

申请日：2019-12-19

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Curtis M. Grens ,  Richard L. Harwood ,  Gary M. Madison

IPC: H03L7/099 ,  H03L7/107 ,  H03L7/093

Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

公开(公告)号：US09748961B2

公开(公告)日：2017-08-29

申请号：US15099757

申请日：2016-04-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Lawrence J. Kushner

IPC: H03L7/197 ,  H03M7/30

CPC classification number: H03L7/1974 ,  H03L7/1976 ,  H03M7/3033

Abstract: Techniques are disclosed for managing the timing between two asynchronous clocks. The techniques are particularly well-suited for synchronizing the reference clock with the divided clock in a phase coherent DSM PLL application, but can be more broadly applied to any application that includes a need for synchronizing a data bus across a clock boundary. In one example embodiment, the techniques are implemented in a retime word circuit operatively coupled between a DSM and the divide-by-N integer divider of a PLL application. The retime word circuit receives the divide word from the DSM and generates a retimed divide word that can be applied to the divider. The retime word circuit maintains the reference clock frequency throughput, and forces the divide word seen by the divider to change only at end of a given divide cycle.

公开(公告)号：US09479185B2

公开(公告)日：2016-10-25

申请号：US14968180

申请日：2015-12-14

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Steven E. Turner

IPC: H03L7/06 ,  H03L7/18 ,  H03M7/30

CPC classification number: H03L7/1806 ,  H03L7/1976 ,  H03M7/3033

Abstract: A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

Abstract translation: 用于维持合成频率的相位相干分数N锁相环合成器包括具有多个前馈累加器级的相位相干Δ-Σ调制器（DSM）。 DSM可操作地耦合到被配置为生成循环参考信号的参考时钟。 DSM被配置为对参考信号的多个周期进行计数，以在每个参考信号周期使DSM的每个级累积DSM的前一级的和，并将每个和乘以 一个分数除法字以产生乘法器输出，从而使得DSM输出与参考时钟一起跟踪的信号序列。