公开(公告)号：US11757458B1

公开(公告)日：2023-09-12

申请号：US17692246

申请日：2022-03-11

申请人： Cadence Design Systems, Inc.

发明人： Vineeth Anavangot ,  Riju Biswas

IPC分类号： H03D3/24 ,  H03L7/18 ,  H03L7/099 ,  H04L7/033

CPC分类号： H03L7/1806 ,  H03L7/099 ,  H04L7/033

摘要： In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

公开(公告)号：US09602115B1

公开(公告)日：2017-03-21

申请号：US15174871

申请日：2016-06-06

申请人： MOTOROLA SOLUTIONS, INC.

发明人： Mark Rozental ,  Ricardo Franco ,  Claudine Tordjman ,  Richard S. Young

IPC分类号： H03L7/06 ,  H03L7/099 ,  H03L7/093 ,  H03L7/095 ,  H03L7/089 ,  H03K5/15 ,  H03L7/18

CPC分类号： H03L7/0996 ,  H03K5/15046 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/18 ,  H03L7/1806

摘要： A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

公开(公告)号：US20160173111A1

公开(公告)日：2016-06-16

申请号：US14968180

申请日：2015-12-14

申请人： BAE SYSTEMS Information and Electronic Systems Integration Inc.

发明人： Joseph D. Cali ,  Steven E. Turner

IPC分类号： H03L7/18 ,  H03M3/00

CPC分类号： H03L7/1806 ,  H03L7/1976 ,  H03M7/3033

摘要： A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

摘要翻译： 用于维持合成频率的相位相干分数N锁相环合成器包括具有多个前馈累加器级的相位相干Δ-Σ调制器（DSM）。 DSM可操作地耦合到被配置为生成循环参考信号的参考时钟。 DSM被配置为对参考信号的多个周期进行计数，以在每个参考信号周期使DSM的每个级累积DSM的前一级的和，并将每个和乘以 一个分数除法字以产生乘法器输出，从而使得DSM输出与参考时钟一起跟踪的信号序列。

公开(公告)号：US08957796B2

公开(公告)日：2015-02-17

申请号：US14507563

申请日：2014-10-06

申请人： IQ-Analog Corporation

发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03L7/091

CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

公开(公告)号：US20150015313A1

公开(公告)日：2015-01-15

申请号：US14503656

申请日：2014-10-01

申请人： IQ-Analog Corporation

发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

IPC分类号： H03L7/091 ,  H03L7/097 ,  H03L7/093

CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

公开(公告)号：US20100225408A1

公开(公告)日：2010-09-09

申请号：US12397060

申请日：2009-03-03

申请人： Ahmadreza Rofougaran ,  Maryam Rofougaran

发明人： Ahmadreza Rofougaran ,  Maryam Rofougaran

IPC分类号： G01D5/20

CPC分类号： H01L23/49822 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15321 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1268 ,  H03B5/1296 ,  H03B2200/0048 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03L7/085 ,  H03L7/099 ,  H03L7/1806 ,  H01L2224/0401

摘要： Methods and systems for VCO impedance control to optimize performance, efficiency, and power consumption are disclosed and may include selectively coupling one of a plurality of taps on a multi-tap inductive load to a voltage controlled oscillator (VCO) on a chip comprising a plurality of transmitters and receivers. The multi-tap inductive load may comprise a multi-tap transformer or transmission line, which may be integrated on the chip, or may be integrated on a package to which the chip is coupled. A voltage swing at an output of the VCO and/or a current in the VCO may be adjusted by configuring a load of the VCO utilizing the multi-tap inductive load. The multi-tap inductive load may be coupled to the VCO utilizing one or more CMOS switches.

摘要翻译： 公开了用于优化性能，效率和功率消耗的VCO阻抗控制的方法和系统，并且可以包括选择性地将多抽头电感性负载上的多个抽头之一耦合到包括多个电感的芯片上的压控振荡器（VCO） 的发射机和接收机。 多抽头电感负载可以包括可以集成在芯片上的多抽头变压器或传输线，或者可以集成在芯片耦合到的封装上。 可以通过利用多抽头电感负载来配置VCO的负载来调整VCO的输出端和/或VCO中的电流的电压摆幅。 多抽头电感负载可以利用一个或多个CMOS开关耦合到VCO。

公开(公告)号：US20100123482A1

公开(公告)日：2010-05-20

申请号：US12346269

申请日：2008-12-30

申请人： Walter Marton ,  Robert Braun

发明人： Walter Marton ,  Robert Braun

IPC分类号： H03D13/00 ,  H03B21/00 ,  H03B19/00

CPC分类号： H03L7/10 ,  H03L7/0891 ,  H03L7/1806 ,  H03L7/193 ,  H03L7/1974

摘要： Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising a reference input configured to receive a reference signal; a feedback input configured to receive a divided signal from divider circuitry in a feedback path of the phase-locked loop; and pulse generation circuitry configured to generate control pulses for controlling a charge pump in the phase-locked loop in accordance with a frequency and phase relationship between the reference signal and the divided signal; wherein the divided signal comprises a pulse having a length shorter than a half period of the divided signal, and wherein the pulse generation circuitry is configured to generate the control pulses by masking the reference signal using the pulse of the divided signal as a mask, so as to define the edges of the control pulses from the edges of the divided signal and an edge of the reference signal.

摘要翻译： 用于锁相环频率合成器的相位检测器电路，所述相位检测器电路包括被配置为接收参考信号的参考输入; 反馈输入，被配置为在所述锁相环的反馈路径中从分频器电路接收分频信号; 以及脉冲发生电路，其被配置为根据所述参考信号和所述分频信号之间的频率和相位关系产生用于控制所述锁相环中的电荷泵的控制脉冲; 其中，所述分割信号包括长度短于所述划分信号的半周期的脉冲，并且其中所述脉冲产生电路被配置为通过使用所述分频信号的脉冲作为掩码来掩蔽所述参考信号来产生所述控制脉冲，因此 以便从划分的信号的边缘和参考信号的边缘定义控制脉冲的边缘。

公开(公告)号：US07557662B2

公开(公告)日：2009-07-07

申请号：US11905815

申请日：2007-10-04

申请人： Seiji Heike ,  Tomihiro Hashizume

发明人： Seiji Heike ,  Tomihiro Hashizume

IPC分类号： H03L7/00

CPC分类号： H03L7/18 ,  H03L7/1806

摘要： In an oscillating apparatus or a frequency detecting apparatus in which a center frequency and a variable frequency range are freely or optionally established with a high stability and a high accuracy, a first frequency component of a signal from a first crystal oscillator and a second frequency component of another signal from a second crystal oscillator are subjected to a synthesizing operation in a synthesizer and to other operations to obtain a desired center frequency and a desired variable frequency range.

摘要翻译： 在以高稳定性和高精度自由地或可选地建立中心频率和可变频率范围的振荡装置或频率检测装置中，来自第一晶体振荡器和第二频率分量的信号的第一频率分量 来自第二晶体振荡器的另一信号经过合成器中的合成操作和其他操作以获得期望的中心频率和期望的可变频率范围。

公开(公告)号：US20090085673A1

公开(公告)日：2009-04-02

申请号：US11863531

申请日：2007-09-28

申请人： Ahmadreza Rofougaran

发明人： Ahmadreza Rofougaran

IPC分类号： H03L7/18 ,  H03L7/16

CPC分类号： H03L7/1806 ,  H03L7/0891

摘要： Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.

摘要翻译： 提供了通过具有DDFS反馈路径的PLL产生信号的方法和系统的方面。 在这方面，可以利用参考信号和反馈信号之间的相位差来控制VCO，其中反馈信号由DDFS产生。 产生的反馈信号的电压，电流和/或功率电平可以被限制在确定的值范围内。 此外，反馈信号可以基于VCO的输出和输入到DDFS的数字控制字。 数字控制字可以由例如处理器编程控制。 另外，可以基于产生的反馈信号的期望频率和VCO的期望输出频率来确定控制字。 因此，DDFS可以由VCO的输出或VCO输出的分频版本来计时。

公开(公告)号：US20080192877A1

公开(公告)日：2008-08-14

申请号：US12029456

申请日：2008-02-11

申请人： Oren E. Eliezer ,  Manouchehr Entezari ,  Robert B. Staszewski ,  Sumeer Bhatara

发明人： Oren E. Eliezer ,  Manouchehr Entezari ,  Robert B. Staszewski ,  Sumeer Bhatara

IPC分类号： H04L7/00

CPC分类号： H03L7/1806 ,  H03L2207/50

摘要： A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.

摘要翻译： 一种新颖有用的装置和方法，其通过调整干扰信号的相位来最小化干扰对整个信道的锁相环（PLL）中的相位误差性能的影响，使得其对参考信号的影响最小化。 通过使用ADPLL的数字架构实现相位控制，并且对其数字化表示的输出和参考相位信号之间引入的任意相位偏置不敏感。 通过校准程序确定每个整数通道的最佳相位关系，其中扫描相位并记录最佳相位。 在整数通道上传输有效负载之前，输出RF信号和输入参考信号之间的相位关系被调整为基于在校准过程中先前记录的值而针对该频率发现的最佳值。