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公开(公告)号：US11303287B1
公开(公告)日：2022-04-12
申请号：US17188518
申请日：2021-03-01
Inventor： Steven E. Turner , Joseph D. Cali
Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.
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Patent Agency Ranking
12.发明申请MODIFIED DELTA-SIGMA MODULATOR FOR PHASE COHERENT FREQUENCY SYNTHESIS APPLICATIONS 有权用于相位频率合成应用的改进型DELTA-SIGMA调制器公开(公告)号：US20160173111A1
公开(公告)日：2016-06-16
申请号：US14968180
申请日：2015-12-14
Inventor： Joseph D. Cali , Steven E. Turner
CPC classification number: H03L7/1806 , H03L7/1976 , H03M7/3033
Abstract: A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.
Abstract translation: 用于维持合成频率的相位相干分数N锁相环合成器包括具有多个前馈累加器级的相位相干Δ-Σ调制器（DSM）。 DSM可操作地耦合到被配置为生成循环参考信号的参考时钟。 DSM被配置为对参考信号的多个周期进行计数，以在每个参考信号周期使DSM的每个级累积DSM的前一级的和，并将每个和乘以 一个分数除法字以产生乘法器输出，从而使得DSM输出与参考时钟一起跟踪的信号序列。
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公开(公告)号：US10698441B2
公开(公告)日：2020-06-30
申请号：US15984841
申请日：2018-05-21
Inventor： Joseph D. Cali , Steven E. Turner
Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.
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公开(公告)号：US10193646B2
公开(公告)日：2019-01-29
申请号：US15608640
申请日：2017-05-30
Inventor： Steven E. Turner
Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.
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公开(公告)号：US20180351677A1
公开(公告)日：2018-12-06
申请号：US15608640
申请日：2017-05-30
Inventor： Steven E. Turner
CPC classification number: H04J3/0685 , G06F1/10 , H03K3/012 , H04J3/047 , H04W56/0015
Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.
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公开(公告)号：US20160028350A1
公开(公告)日：2016-01-28
申请号：US14808653
申请日：2015-07-24
Inventor： Steven E. Turner , Michael P. Anthony
CPC classification number: H03K5/131 , G06F1/08 , H03K2005/00058
Abstract: According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock.
Abstract translation: 根据实施例，改进的飞行加法器电路包括精细时钟，粗略脉冲时钟，连接到精细时钟和粗略脉冲时钟的上升沿触发输出，连接到上升沿触发输出的脉冲时钟， 加法器，用于接收来自加法器和脉冲时钟的信号的12位寄存器，以及用于从脉冲时钟接收信号的单个位寄存器。
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