公开(公告)号：US20250148995A1

公开(公告)日：2025-05-08

申请号：US19013194

申请日：2025-01-08

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Zhenzhen Shan ,  Jianchao Zhu ,  Guangliang Shang ,  Xing Yao

IPC: G09G3/3266

Abstract: A display substrate includes a scan circuit, a first reference signal line in a third region, and at least three clock signal lines arranged in a fourth region. The scan circuit includes a plurality of stages, wherein a respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node.

公开(公告)号：US12283246B2

公开(公告)日：2025-04-22

申请号：US17636898

申请日：2021-03-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Libin Liu ,  Li Wang ,  Xinshe Yin ,  Shiming Shi

IPC: G09G3/3266 ,  G11C19/28

Abstract: Provided is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units; a shift register unit includes an input sub-circuit and a denoising output sub-circuit. The denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines. The third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction.

公开(公告)号：US12230216B2

公开(公告)日：2025-02-18

申请号：US18245534

申请日：2022-05-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Zhenzhen Shan ,  Jianchao Zhu ,  Guangliang Shang ,  Xing Yao

IPC: G09G3/32 ,  G09G3/3266

Abstract: A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive a start signal or an output signal from a previous scan unit, a first processing subcircuit, a second processing subcircuit, and an output subcircuit. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node. The first node is coupled to a gate electrode of the first output transistor. The first processing subcircuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

公开(公告)号：US12223908B2

公开(公告)日：2025-02-11

申请号：US18262598

申请日：2022-08-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhenzhen Shan ,  Libin Liu ,  Jiangnan Lu ,  Shiming Shi

IPC: G09G3/3258 ,  G09G3/32 ,  G09G3/3233 ,  G09G3/3266 ,  G11C19/28 ,  H01L27/12 ,  H01L21/77

Abstract: A display substrate includes a pixel driving circuit, which includes a driving circuit, a storage circuit and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit. The driving circuit is used to conduct a path between the first terminal and a second terminal of the driving circuit under the control of a potential at its control terminal. The storage circuit is electrically connected to the control terminal of the driving circuit. The reset circuit includes a first capacitor. The storage circuit includes a second capacitor. An area of an overlap between orthographic projections of a first electrode plate and a second electrode plate of the first capacitor on the base substrate is smaller than that of the second capacitor on the base substrate.

公开(公告)号：US12205540B2

公开(公告)日：2025-01-21

申请号：US17764395

申请日：2021-03-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Xinshe Yin ,  Libin Liu ,  Jianchao Zhu ,  Hao Zhang ,  Ke Feng

IPC: G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.

公开(公告)号：US12108643B2

公开(公告)日：2024-10-01

申请号：US17953941

申请日：2022-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Can Zheng ,  Yu Feng ,  Libin Liu ,  Jie Zhang ,  Mei Li

IPC: H10K59/131 ,  G09G3/3208 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/121 ,  G09G3/3208 ,  G09G2320/0209 ,  G09G2320/0233

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US11937465B2

公开(公告)日：2024-03-19

申请号：US17630908

申请日：2021-03-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Libin Liu ,  Jiangnan Lu

IPC: H10K59/124 ,  G09G3/3233

CPC classification number: H10K59/124 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2320/0233

Abstract: Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof. The array substrate includes a substrate and a plurality of sub-pixels on the substrate. Each sub-pixel includes a pixel circuit. The pixel circuit includes a plurality of transistors. The plurality of transistors includes at least one oxide transistor. The array substrate further includes: an oxide semiconductor layer on the substrate, the oxide semiconductor layer comprising a channel region of the oxide transistor; a first planarization layer on the substrate and covering at least a portion of the oxide semiconductor layer; a barrier part on the side of the first planarization layer away from the substrate.

公开(公告)号：US11854489B2

公开(公告)日：2023-12-26

申请号：US17610043

申请日：2021-01-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiangnan Lu ,  Can Zheng

IPC: G09G5/00 ,  G09G3/3266 ,  G11C19/28 ,  H10K59/131

CPC classification number: G09G3/3266 ,  G11C19/28 ,  H10K59/131 ,  G09G2300/0852 ,  G09G2310/0286

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

公开(公告)号：US11798458B2

公开(公告)日：2023-10-24

申请号：US17905620

申请日：2021-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jie Zhang ,  Jiangnan Lu ,  Mei Li ,  Libin Liu

IPC: G09G3/3266 ,  G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2330/021

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.

公开(公告)号：US20200152124A1

公开(公告)日：2020-05-14

申请号：US16619224

申请日：2018-12-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  Beihang University

Inventor： Hongge Li ,  Yuliang Li ,  Jiangnan Lu

IPC: G09G3/3233

Abstract: A pixel circuit configured to drive a light-emitting element and a driving method therefor, and a display substrate, the pixel circuit comprising: a first switch sub-circuit configured to input, under the control of a first control signal line, a data signal of a data signal line to a first node; a second switch sub-circuit configured to input, under the control of a second control signal line, a first signal of a first signal line to a second node; a driving sub-circuit configured to drive, under the control of the potential of the first node, the light-emitting element to emit light; and a memory sub-circuit configured to store a threshold voltage of the driving sub-circuit before the second switch sub-circuit is turned on in each work cycle of the pixel circuit.