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公开(公告)号：US12108643B2
公开(公告)日：2024-10-01
申请号：US17953941
申请日：2022-09-27
发明人： Jiangnan Lu , Guangliang Shang , Can Zheng , Yu Feng , Libin Liu , Jie Zhang , Mei Li
IPC分类号： H10K59/131 , G09G3/3208 , H10K59/121
CPC分类号： H10K59/131 , H10K59/121 , G09G3/3208 , G09G2320/0209 , G09G2320/0233
摘要： Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.
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公开(公告)号：US11937465B2
公开(公告)日：2024-03-19
申请号：US17630908
申请日：2021-03-11
发明人： Libin Liu , Jiangnan Lu
IPC分类号： H10K59/124 , G09G3/3233
CPC分类号： H10K59/124 , G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0233
摘要： Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof. The array substrate includes a substrate and a plurality of sub-pixels on the substrate. Each sub-pixel includes a pixel circuit. The pixel circuit includes a plurality of transistors. The plurality of transistors includes at least one oxide transistor. The array substrate further includes: an oxide semiconductor layer on the substrate, the oxide semiconductor layer comprising a channel region of the oxide transistor; a first planarization layer on the substrate and covering at least a portion of the oxide semiconductor layer; a barrier part on the side of the first planarization layer away from the substrate.
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公开(公告)号：US11854489B2
公开(公告)日：2023-12-26
申请号：US17610043
申请日：2021-01-13
发明人： Jiangnan Lu , Can Zheng
IPC分类号： G09G5/00 , G09G3/3266 , G11C19/28 , H10K59/131
CPC分类号： G09G3/3266 , G11C19/28 , H10K59/131 , G09G2300/0852 , G09G2310/0286
摘要： A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.
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公开(公告)号：US11798458B2
公开(公告)日：2023-10-24
申请号：US17905620
申请日：2021-08-12
发明人： Guangliang Shang , Jie Zhang , Jiangnan Lu , Mei Li , Libin Liu
IPC分类号： G09G3/3266 , G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0426 , G09G2300/0842 , G09G2310/0267 , G09G2330/021
摘要： A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.
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5.发明申请公开(公告)号：US20200152124A1
公开(公告)日：2020-05-14
申请号：US16619224
申请日：2018-12-03
发明人： Hongge Li , Yuliang Li , Jiangnan Lu
IPC分类号： G09G3/3233
摘要： A pixel circuit configured to drive a light-emitting element and a driving method therefor, and a display substrate, the pixel circuit comprising: a first switch sub-circuit configured to input, under the control of a first control signal line, a data signal of a data signal line to a first node; a second switch sub-circuit configured to input, under the control of a second control signal line, a first signal of a first signal line to a second node; a driving sub-circuit configured to drive, under the control of the potential of the first node, the light-emitting element to emit light; and a memory sub-circuit configured to store a threshold voltage of the driving sub-circuit before the second switch sub-circuit is turned on in each work cycle of the pixel circuit.
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公开(公告)号：US12062311B2
公开(公告)日：2024-08-13
申请号：US17795033
申请日：2021-08-30
发明人： Hao Zhang , Jiangnan Lu
CPC分类号： G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286
摘要： Provided is a display panel. The display panel includes a substrate including a display region and a non-display region surrounding the display region; and a shift register unit, disposed in the non-display region; wherein the shift register unit includes a first shift circuit and a second shift circuit; wherein the first shift circuit is coupled to a first clock terminal, a second clock terminal, an input signal terminal, a first power terminal, a second power terminal, and a shift node; and the second shift circuit is coupled to the shift node, the first clock terminal, the second clock terminal, a third clock terminal, an enable control terminal, an output control terminal, the first power terminal, the second power terminal, and an output terminal.
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公开(公告)号：US20240161669A1
公开(公告)日：2024-05-16
申请号：US17781988
申请日：2021-03-24
发明人： Jiangnan Lu , Guangliang Shang , Libin Liu , Long Han , Yu Feng
CPC分类号： G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0233 , G09G2330/021
摘要： A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.
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8.发明公开公开(公告)号：US20230343285A1
公开(公告)日：2023-10-26
申请号：US17764395
申请日：2021-03-18
发明人： Jiangnan Lu , Guangliang Shang , Xinshe Yin , Libin Liu , Jianchao Zhu , Hao Zhang , Ke Feng
IPC分类号： G09G3/3233 , G11C19/28
CPC分类号： G09G3/3233 , G11C19/28 , G09G2310/0286 , G09G2300/0842 , G09G2310/08
摘要： A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.
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公开(公告)号：US11587983B2
公开(公告)日：2023-02-21
申请号：US16959376
申请日：2019-07-31
发明人： Kaipeng Sun , Yuanyou Qiu , Weiyun Huang , Yue Long , Chao Zeng , Jiangnan Lu , Libin Liu , Hongli Wang
IPC分类号： H01L27/32
摘要： An electroluminescent display panel includes a plurality of repeating units each including a first conductive layer, a first insulating layer including a first via hole, and an anode including a main body and an auxiliary portion. At least one repeating unit includes a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel; the area of the main body of the third-color sub-pixel is larger than that of the second-color sub-pixel and that of the first-color sub-pixel; and an overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the second-color sub-pixel and the first conductive layer, and the overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the first-color sub-pixel and the first conductive layer.
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公开(公告)号：US11320691B2
公开(公告)日：2022-05-03
申请号：US16508833
申请日：2019-07-11
发明人： Jiangnan Lu , Shi Shu , Kang Guo , Qi Yao
IPC分类号： G02F1/1335 , G02B5/30 , G02F1/1333 , G02F1/1368 , G02F1/1334
摘要： Provided are a manufacturing method of a display substrate, a display substrate and a display device, which belongs to the field of display technologies. The manufacturing method of the display substrate includes: forming a first planarization layer on a base substrate on which a patterned film layer is formed; forming a first buffer layer on the side, away from the base substrate, of the first planarization layer; forming a second buffer layer on the side, away from the base substrate, of the first buffer layer; and forming a Wire Grid Polarizer (WGP) on the side, away from the base substrate, of the second buffer layer.
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