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公开(公告)号：US12154496B2
公开(公告)日：2024-11-26
申请号：US18270850
申请日：2021-02-26
Inventor： Shaolei Zong , Jigang Sun , Rui Liu , Xin Duan , Wei Sun , Junwei Zhang , Hongrun Wang , Fuqiang Li , Changfeng Sun , Hui Zhang , Xue Dong
IPC: G09G3/3225 , G09G3/20 , G09G3/36 , H04N23/611 , H04N23/67
Abstract: Disclosed are a display panel, a display device and a driving method. The display panel includes a plurality of sub-pixel units located in areas formed by the plurality of scanning signal lines and the plurality of data signal lines, and at least two adjacent sub-pixel units in the first direction and the second direction constitute a pixel island. A plurality of control units each corresponding to a sub-pixel unit row in the pixel island are provided. The control unit includes a control terminal, an input terminal and an output terminal. The control unit is configured to transmit a signal from the input terminal to the output terminal under control of a first signal transmitted by a control signal line corresponding to the control unit, and stop transmitting the signal from the input terminal to the output terminal under control of a second signal transmitted by the control signal line.
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公开(公告)号：US12131683B2
公开(公告)日：2024-10-29
申请号：US17497920
申请日：2021-10-09
Inventor： Xin Duan , Jigang Sun , Shaolei Zong , Wei Sun
CPC classification number: G09G3/2092 , G06F1/08 , G06F1/12 , G06F1/14 , G09G2310/08 , G09G2340/0435
Abstract: A method for clock calibration is provided. In the technical solution according to the present disclosure, a target driving chip includes a plurality of clock calibration circuits, wherein each of the clock calibration circuits is configured with one clock frequency. Prior to sending a clock calibration signal, a controller sends a reference clock frequency to a driving chip over a configuration instruction, such that the driving chip determines a target clock calibration circuit for clock calibration based on the configuration instruction.
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公开(公告)号：US11715441B2
公开(公告)日：2023-08-01
申请号：US17362944
申请日：2021-06-29
Inventor： Wenyu Li , Jinghua Miao , Lili Chen , Hao Zhang , Shaolei Zong , Xin Duan , Jigang Sun , Wei Sun
CPC classification number: G09G5/02 , G09G5/003 , G09G2300/0804 , G09G2300/0828 , G09G2310/0297 , G09G2330/028
Abstract: Provided are a virtual reality display device, a host device, a system and a data processing method. The virtual reality display device includes a display panel and a drive chip, wherein the drive chip includes a first processing module and a drive module; the first processing module is configured to decode an image to be decoded with a third color depth sent by a second processing module in a virtual reality host device to obtain a first image with a first color depth and a second image with a second color depth, the third color depth is greater than or equal to the first color depth, and the second color depth is less than the first color depth; the drive module is configured to generate a first data voltage corresponding to the first image and a second data voltage corresponding to the second image.
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公开(公告)号：US10706759B2
公开(公告)日：2020-07-07
申请号：US16096607
申请日：2018-05-15
Inventor： Yaran Wang , Wei Zhang , Jigang Sun , Wei Sun
IPC: G09G3/20
Abstract: A current comparison circuit for use in a display device. The display device is configured to be supplied with a plurality of power supply voltages for powering a digital portion and an analog portion of the display device through respective power supplying paths. The current comparison circuit includes a plurality of comparator circuits, each of which is configured to compare a current on a respective one of the power supplying paths with a respective reference value and to output the respective comparison value. A combination of the respective comparison values output by the comparator circuits indicates a type of content being displayed by the display device.
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公开(公告)号：US12087245B2
公开(公告)日：2024-09-10
申请号：US18037043
申请日：2020-11-20
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shaolei Zong , Jigang Sun , Weixin Jiang , Bin Wang , Wei Sun , Xin Duan , Shuhuan Yu , Kexin Hao , Jiaqi Fan , Zhaoyun Gu , Shaoru Zhang , Tieshi Wang , Kuanjun Peng , Xue Dong , Wei Qin , Weixing Liu
IPC: G09G3/36 , G06T15/00 , H04N13/383
CPC classification number: G09G3/3674 , G06T15/00 , H04N13/383 , G09G2354/00
Abstract: A display apparatus and a driving method therefor. The driving method includes: determining a gaze area and a non-gaze area of a user on a display apparatus in real time (S10); and driving the gaze area for image displaying at a first resolution, and driving the non-gaze area for image displaying at a second resolution, wherein the first resolution is higher than the second resolution. By using of the display apparatus, image resolution can be adjusted according to different areas, so as to realize high-resolution image display in a display area at which a user gazes and realize low-resolution image display in other areas, thereby reducing power consumption and achieving reasonable allocation of resources on the premise of ensuring the user experience.
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Patent Agency Ranking
公开(公告)号：US12033586B2
公开(公告)日：2024-07-09
申请号：US18273041
申请日：2022-08-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shaolei Zong , Wei Sun , Rui Liu , Jigang Sun , Kuanjun Peng
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2300/0842 , G09G2310/0286 , G09G2310/061
Abstract: A display panel, a gate drive circuit and a driving method thereof. The gate drive circuit includes drive units. A first cascaded input end OUT(n−1) of a first shift register (100) of each of the drive units is connected to a different start signal end STV; a plurality of drive units in the drive units include a reset control sub-circuit (9), where the reset control sub-circuit (9) is connected with a second cascaded input end OUT(n+1) of a last shift register (100) and one or more start signal ends STV, and is configured to control an electric potential of the second cascaded input end OUT(n−1) according to an electric potential of the one or more start signal ends STV.
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公开(公告)号：US11776443B2
公开(公告)日：2023-10-03
申请号：US17052251
申请日：2020-04-08
Inventor： Jing Zhao , Xu Su , Shuang Zhao , Jigang Sun
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2300/0408 , G09G2310/0267 , G09G2310/08 , G09G2330/021
Abstract: There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an nth stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n−1)th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1)th stage, n is an integer greater than 1.
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公开(公告)号：US11574575B2
公开(公告)日：2023-02-07
申请号：US17555153
申请日：2021-12-17
Inventor： Shaolei Zong , Jigang Sun , Rui Liu , Wei Sun , Xin Duan , Junwei Zhang
Abstract: Provided are a shift register unit, a shift register, a display panel and a driving method thereof. The shift register unit includes: an input circuit electrically coupled to an input terminal, a first voltage terminal and a pull-up node; an output circuit electrically coupled to the pull-up node, a first clock terminal, a first scan control terminal, a first output terminal and a second output terminal; and a scan control circuit electrically coupled to the second output terminal, a second voltage terminal and a second scan control terminal. The input circuit is configured to write a first voltage provided by the first voltage terminal into the pull-up node in response to a start signal inputted to the input terminal. The output circuit is configured to output a first clock signal from the first clock terminal via the first output terminal, when the pull-up node is at the first voltage.
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公开(公告)号：US11157227B2
公开(公告)日：2021-10-26
申请号：US16641298
申请日：2019-03-18
Inventor： Yanfei Ren , Jigang Sun , Wanhua Yang , Weixing Shan , Shaolei Zong
IPC: G06F3/14 , G06F3/041 , G09G3/3225 , G09G3/36
Abstract: A switching control device, a control method, and a display device are provided. The switching control device includes: a main control circuit and switch control circuits in one-to-one correspondence with display screens. The main control circuit is configured to output a display control voltage, and output in a time-division manner a display switching instruction in one-to-one correspondence with each of the display screens. For each of the display screens, the display switching instruction includes: a switch control signal, a data signal, a lighting signal, and an extinguishing signal. The main control circuit is configured to output a lighting signal to the corresponding display screens, and to output an extinguishing signal to the corresponding display screens. The switch control circuits are configured to receive a display control voltage and a switch control signal, and supply a display control voltage to the corresponding display screens.
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20.发明授权公开(公告)号：US12033554B2
公开(公告)日：2024-07-09
申请号：US17627143
申请日：2021-04-12
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shaolei Zong , Jigang Sun , Chingwen Kung , Wei Sun
CPC classification number: G09G3/20 , G11C19/28 , G09G3/2092 , G09G3/3674 , G09G3/3677 , G09G2310/0202 , G09G2310/0267 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2354/00
Abstract: A shift register, a gate drive circuit, a display device, and a driving method for the same. The shift register comprises a first output sub-circuit, which provides, under control of an INPUT or a RESET, a signal of a CN or a CNB to a pull-up node, outputs, according to a voltage level of the pull-up node, a signal of a CK to an OUT, transmits, under control of a CKB, a CKB to a pull-down node, and pulls down, according to a voltage level of the pull-down node, a voltage level of the OUT; a second output sub-circuit, which outputs, during a scan output stage and under control of a GON, a signal of the OUT to a GOUT; and a transfer sub-circuit, which pulls down, during a scan transfer stage and under control of a GOFF, a voltage level of the GOUT.
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