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11.发明申请公开(公告)号：US20150380471A1
公开(公告)日：2015-12-31
申请号：US14495219
申请日：2014-09-24
Inventor： Renwei GUO , Xue DONG , Peng LIU
CPC classification number: H01L27/3218 , G09G3/20 , G09G3/3208 , G09G2300/0439 , G09G2300/0443 , G09G2300/0465
Abstract: A pixel arrangement structure according to the present disclosure may include pixel units parallel to each other. The pixel units each includes a plurality of first pixels and second pixels spaced from each other. The first pixels each include a first sub-pixel located in a first row, a second sub-pixel located in a second row, and a third sub-pixel located in third and fourth rows. The second pixels each include a third sub-pixel located in the first and second rows, a first sub-pixel located in the third row, and a second sub-pixel located in the fourth row. The first sub-pixels and second sub-pixels are arranged horizontally, while the third sub-pixels are arranged longitudinally.
Abstract translation: 根据本公开的像素排列结构可以包括彼此平行的像素单元。 像素单元各自包括彼此间隔开的多个第一像素和第二像素。 第一像素每个包括位于第一行中的第一子像素，位于第二行中的第二子像素和位于第三行和第四行的第三子像素。 第二像素各自包括位于第一行和第二行中的第三子像素，位于第三行中的第一子像素和位于第四行中的第二子像素。 第一子像素和第二子像素被水平布置，而第三子像素被纵向布置。
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公开(公告)号：US20250131968A1
公开(公告)日：2025-04-24
申请号：US18689081
申请日：2022-08-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhichong WANG , Peng LIU , Jing FENG
IPC: G11C19/28 , G09G3/3233 , H10K59/131
Abstract: Disclosed is a shift register, comprising: a first control sub-circuit, which provides a signal of a signal input end for a first node; a second control sub-circuit, which provides a signal of a second power source end or a signal of the first clock signal end for the second node; a third control sub-circuit, which provides a signal of the second clock signal end or a signal of the first power source end for a fourth node and maintains the potential of the fourth node; a first output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a first signal output end; and a second output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a second signal output end.
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公开(公告)号：US20250061860A1
公开(公告)日：2025-02-20
申请号：US18724736
申请日：2021-12-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhichong WANG , Jing FENG , Peng LIU
IPC: G09G3/3258
Abstract: A pixel group includes a plurality of pixel circuits and a compensation circuit; where each of the pixel circuits is connected to the compensation circuit; each of the pixel circuits includes a driving transistor; the compensation circuit includes a third transistor; and the compensation circuit is capable of loading a threshold voltage of the third transistor to a control end of the driving transistor; and a channel region of the third transistor has a width to length ratio of a3, a channel region of the driving transistor has a width to length ratio of a1, and a3/a1 is in a range of 1-1.05.
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公开(公告)号：US20240353720A1
公开(公告)日：2024-10-24
申请号：US18028523
申请日：2022-03-31
Inventor： Peirong HUO , Chao LIANG , Peng LIU , Jingyi XU , Bo LI , Zhenhong XIAO
IPC: G02F1/1362
CPC classification number: G02F1/136286 , G02F1/136218
Abstract: An array substrate and a display device are provided. The array substrate includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.
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公开(公告)号：US20240231163A1
公开(公告)日：2024-07-11
申请号：US17911491
申请日：2021-10-25
Inventor： Peirong HUO , Bo LI , Peng LIU , Yongqiang ZHANG , Jingyi XU
IPC: G02F1/1362 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/136209 , G02F1/136286 , G02F1/1368 , H01L27/124
Abstract: The array base plate includes a plurality of sub-pixels that are arranged in an array; each of the sub-pixels includes a light shielding layer, a semiconductor layer, a grid layer, a source-drain layer and a pixel electrode layer that are arranged in layer configuration on the substrate sequentially; the semiconductor layer includes a first contacting part, a first channel part, a doping part, a second channel part and a second contacting part that are sequentially connected; the grid layer includes a first grid electrode and a second grid electrode; the source-drain layer includes a first electrode and a second electrode; and an orthographic projection of the light shielding layer on the substrate at least covers orthographic projections on the substrate of the first channel part, the second channel part and a part of the first contacting part.
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Patent Agency Ranking
公开(公告)号：US20220178013A1
公开(公告)日：2022-06-09
申请号：US17680478
申请日：2022-02-25
Inventor： Jinbiao LIU , Luoyang FENG , Youliang LI , Tianyu XU , Rui TAN , Yongyong WEI , Xiang LIU , Li CHEN , Kai WEN , Qinwen JIANG , Shangshu SUN , Peng LIU
Abstract: An evaporation source includes a crucible, a heater, a heat adjusting assembly for convecting heat radiation between the heat adjusting assembly and the crucible body and including a first reflection plate and a second reflection plate, and a hollowed-out pattern provided in the second reflection plate. The crucible includes a crucible body having a top surface, a bottom surface and side surfaces connecting the top and the bottom surfaces; and a nozzle disposed on the top surface of the crucible body. The heater is disposed outside the crucible body for generating heat radiation. Wherein the first reflection is disposed on at least one side of the side surfaces of the crucible body, a gap exists between the first reflection plate and the crucible body; the second reflection plate is disposed under the bottom surface of the crucible body, a gap exists between the second reflection plate and the crucible body.
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公开(公告)号：US20220157223A1
公开(公告)日：2022-05-19
申请号：US17355637
申请日：2021-06-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhichong WANG , Xinglong LUAN , Peng LIU , Jing FENG , Gaoming SUN , Yi OUYANG
IPC: G09G3/32
Abstract: The present application discloses a pixel circuit and a driving method thereof, and a display device. The circuit includes: a first initialization sub-circuit, a data writing circuit, a light emitting control circuit, a capacitor circuit, a drive transistor, a compensation circuit, a light emitting element, and a holding circuit; the first initialization sub-circuit is connected to a second terminal of the capacitor circuit and a gate of the drive transistor; the data writing circuit and the holding circuit are connected to a first terminal of the capacitor circuit; the light emitting control circuit is connected to a first electrode of the light emitting element and a second electrode of the drive transistor; a first electrode of the drive transistor is connected to the first power supply; a second electrode of the light emitting element is connected to a second power supply.
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公开(公告)号：US20210343242A1
公开(公告)日：2021-11-04
申请号：US17243915
申请日：2021-04-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhichong WANG , Fuqiang LI , Peng LIU , Xinglong LUAN , Jing FENG
IPC: G09G3/3258 , G09G3/3291 , H01L27/32
Abstract: A pixel circuit includes a data writing sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The data writing sub-circuit is connected to the driving sub-circuit, and is configured to write a data voltage signal into the driving sub-circuit and compensate it, in response to a first gate signal and a second gate signal. The light-emitting control sub-circuit is connected to the driving sub-circuit, and is configured to close a line between a first power supply voltage terminal and a second power supply voltage terminal, in response to a first enable signal and a second enable signal. The driving sub-circuit is configured to provide a driving current to a light-emitting device through the closed line according to the written data voltage signal. Phases of the first enable signal and the first gate signal are opposite, and phases of the second enable signal and the second gate signal are opposite.
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公开(公告)号：US20200243013A1
公开(公告)日：2020-07-30
申请号：US16600908
申请日：2019-10-14
Inventor： Zhichong WANG , Fuqiang LI , Jing FENG , Peng LIU , Xinglong LUAN
IPC: G09G3/3258
Abstract: Disclosed are a pixel circuitry, a method for driving the same and a display device. The pixel circuitry includes a light-emitting element, a driving circuit, a compensation control circuit, an initialization circuit, an energy storage circuit, a writing control circuit and a light-emitting control circuit. The driving circuit is configured to drive the light-emitting element to emit light. The initialization circuit is configured to write an initialization voltage to a control end of the driving circuit to control the driving circuit to be turned on or off. The compensation control circuit is configured to turn on the driving circuit and perform threshold voltage compensation on the driving circuit. The writing control circuit is configured to write a data voltage inputted by a data line to a second end of the energy storage circuit and write a reference voltage to the second end of the energy storage circuit.
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公开(公告)号：US20200005881A1
公开(公告)日：2020-01-02
申请号：US16489185
申请日：2018-10-25
Inventor： Peng LIU , Zhen WANG , Han ZHANG , Kai ZHANG , Yun QIAO , Jian SUN , Bailing LIU , Fei HUANG , Zhengkui WANG , Jianjun ZHANG
IPC: G11C19/28 , G09G3/36 , G09G3/3266
Abstract: A shift register includes a first input sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit. The first input sub-circuit is configured to transmit a voltage from the first signal terminal to the first node under control of the first voltage terminal. The pull-up control sub-circuit is configured to be in a turn-on or turn-off state under control of the first node. The pull-down control sub-circuit is configured to transmit a voltage from the third voltage terminal to the pull-down node under control of the first node, transmit the voltage from the third voltage terminal to the pull-down node under control of the signal output terminal, and transmit a voltage from the first clock signal terminal to the pull-down node under control of the first clock signal terminal.
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