公开(公告)号：US20190296152A1

公开(公告)日：2019-09-26

申请号：US16345204

申请日：2018-02-27

Applicant: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Keke GU ,  Ni YANG ,  Hui LI ,  Xin LIU

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/66

Abstract: A thin film transistor includes a gate, an active layer, a source, a drain. The source includes a connecting portion, a first sub-portion, a second sub-portion, and a third sub-portion that are arranged sequentially and in parallel. At first ends of the sub-portions, the connecting portion is connected to the portions to form two adjacent recesses. At second ends of the sub-portions, the distance from an end of the second sub-portion to the connecting portion is smaller than a distance from an end of the first sub-portion to the connecting portion and a distance from an end of the third sub-portion to the connecting portion. The drain includes a connecting block, a first drain and a second drain disposed in the two recesses respectively, and at least a portion of the connecting block is disposed between the first and the second drains to connect the first and the second drains.

公开(公告)号：US20180197896A1

公开(公告)日：2018-07-12

申请号：US15563587

申请日：2017-05-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Keke GU ,  Ni YANG ,  Wei HU ,  Shaoru LI ,  Xin LIU ,  Zhijian QI ,  Yusong HOU

IPC: H01L27/12 ,  G02F1/1362 ,  H01L21/77

CPC classification number: H01L27/1251 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/77 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/41733 ,  H01L2021/775

Abstract: A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.