公开(公告)号：US08704567B2

公开(公告)日：2014-04-22

申请号：US13611008

申请日：2012-09-12

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

公开(公告)号：US08476945B2

公开(公告)日：2013-07-02

申请号：US13069653

申请日：2011-03-23

申请人： Danny Elad ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Danny Elad ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  H03L2207/06

摘要： Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile.

摘要翻译： 公开了相位轮廓发生器系统和方法。 系统包括信号发生器，目标相位轨迹模块，误差检测器和控制环路滤波器。 信号发生器被配置为产生输出信号。 另外，目标相位轨迹模块被配置为跟踪目标相位轨迹，并且确定输出信号的下一个调整以使输出信号符合目标相位轨迹的一部分。 此外，误差检测器被配置为确定输出信号和在目标相位轨迹的部分之前的当前目标相位轨迹值之间的误差，其中误差的确定与输出信号的下一个调整无关。 此外，控制环路滤波器被配置为根据下一个调整和误差来控制信号发生器以产生相位分布。

公开(公告)号：US20100013531A1

公开(公告)日：2010-01-21

申请号：US12173140

申请日：2008-07-15

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/1075 ,  H03L2207/50

摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.

摘要翻译： 提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。 通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分 采用全时钟信号脉冲宽度调制。

公开(公告)号：US07750701B2

公开(公告)日：2010-07-06

申请号：US12173159

申请日：2008-07-15

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/50

摘要： Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

摘要翻译： 提供了电路和方法，其中数字PLL电路中的DCO（数字控制振荡器）电路的微调控制通过在数字控制下对多路复用器电路进行抖动控制来实现，以选择性地输出具有变化的电压电平的多个模拟控制电压中的一个 输入到DCO的分数频率控制端口，以分数频率分辨率驱动DCO的调谐元件，并在模拟控制下实现DCO的连续微调。

公开(公告)号：US08704566B2

公开(公告)日：2014-04-22

申请号：US13608277

申请日：2012-09-10

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

摘要翻译： 提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。 可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。 可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。 可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

公开(公告)号：US20140070856A1

公开(公告)日：2014-03-13

申请号：US13611008

申请日：2012-09-12

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/107

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

摘要翻译： 提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。 可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。 可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。 可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

公开(公告)号：US20100188158A1

公开(公告)日：2010-07-29

申请号：US12358736

申请日：2009-01-23

申请人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Zeynep Toprak Deniz ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/099

CPC分类号： H03L7/081 ,  H03L7/085 ,  H03L7/099

摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.

摘要翻译： 数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。 相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。 数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

公开(公告)号：US20100013532A1

公开(公告)日：2010-01-21

申请号：US12173159

申请日：2008-07-15

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/08

CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/50

摘要： Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control.

摘要翻译： 提供了电路和方法，其中数字PLL电路中的DCO（数字控制振荡器）电路的微调控制通过在数字控制下对多路复用器电路进行抖动控制来实现，以选择性地输出具有变化的电压电平的多个模拟控制电压中的一个 输入到DCO的分数频率控制端口，以分数频率分辨率驱动DCO的调谐元件，并在模拟控制下实现DCO的连续微调。

公开(公告)号：US20140070855A1

公开(公告)日：2014-03-13

申请号：US13608277

申请日：2012-09-10

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/107

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

公开(公告)号：US08665034B2

公开(公告)日：2014-03-04

申请号：US13245409

申请日：2011-09-26

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03B5/08

CPC分类号： H03L7/099 ,  H03L2207/50

摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.

摘要翻译： 公开了用于改进变容二极管电路调谐控制的技术。 例如，一种装置包括用于调谐频率值的多个变容二极管。 多个变容二极管包括大约sqrt（2N）变容二极管，其中N是多个调谐步骤，并且多个变容二极管的尺寸分别为1x，2x，3x，4x。 。 。 ，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。 这可以称为冗余编号。