公开(公告)号：US08788725B2

公开(公告)日：2014-07-22

申请号：US13890229

申请日：2013-05-08

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Elsbeth Lauren Tagayo Villapana ,  Joel Alonzo Baylon

IPC: G06F13/28

CPC classification number: G06F13/1657 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/36

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。

公开(公告)号：US09971524B1

公开(公告)日：2018-05-15

申请号：US14217249

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Avnher Villar Santos ,  Marlon Basa Verdan ,  Elsbeth Lauren Tagayo Villapana

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0656 ,  G06F3/0688

Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.