公开(公告)号：US09916213B1

公开(公告)日：2018-03-13

申请号：US14688209

申请日：2015-04-16

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie De La Cruz Espuerta ,  Marlon Basa Verdan

IPC: G06F13/36 ,  G06F11/20 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F11/2007 ,  G06F11/2002 ,  G06F11/2005 ,  G06F11/2017 ,  G06F11/202 ,  G06F11/2023 ,  G06F11/2041 ,  G06F13/1605 ,  G06F13/366 ,  G06F13/4031

Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

公开(公告)号：US09971524B1

公开(公告)日：2018-05-15

申请号：US14217249

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Avnher Villar Santos ,  Marlon Basa Verdan ,  Elsbeth Lauren Tagayo Villapana

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0656 ,  G06F3/0688

Abstract: An embodiment of the invention provides a method for optimizing flash device accesses, comprising: interleaving and striping, in tandem, for a transfer of data the other portions of the data.

公开(公告)号：US10430303B1

公开(公告)日：2019-10-01

申请号：US15891147

申请日：2018-02-07

Applicant: BITMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Cyrill Coronel Ponce ,  Jarmie Dela Cruz Espuerta ,  Marlon Basa Verdan

IPC: G06F11/20 ,  G06F13/16 ,  G06F13/40

Abstract: In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

公开(公告)号：US09875205B1

公开(公告)日：2018-01-23

申请号：US14217161

申请日：2014-03-17

Applicant: BiTMICRO Networks, Inc.

Inventor： Ricardo H. Bruce ,  Jarmie De La Cruz Espuerta ,  Marlon Basa Verdan

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4031 ,  G06F13/385 ,  G06F13/4027

Abstract: A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.