公开(公告)号：US20150077319A1

公开(公告)日：2015-03-19

申请号：US14373816

申请日：2013-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing Yao ,  Seung Woo Han ,  Jing Lv

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register unit and a driving method and a display apparatus can realize outputting of two gate line signals in one shift register unit, which is convenient to a circuit integration design of products and also facilitates an implementation of a narrow bezel product. The shift register unit comprises a first input module, a second input module, a first gate line driving signal module, a second gate line driving signal module, a pulling-down module and a resetting module.

Abstract translation: 移位寄存器单元和驱动方法和显示装置可以实现在一个移位寄存器单元中输出两个栅极线信号，这便于产品的电路集成设计，并且还有助于实现窄边框产品。 移位寄存器单元包括第一输入模块，第二输入模块，第一栅极线驱动信号模块，第二栅极线驱动信号模块，下拉模块和复位模块。

公开(公告)号：US12236892B2

公开(公告)日：2025-02-25

申请号：US18272595

申请日：2022-07-28

Applicant: Hefei BOE Joint Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Zhidong Yuan ,  Yongqian Li ,  Can Yuan ,  Liu Wu ,  Luke Ding ,  Cheng Xu ,  Miao Liu ,  Xing Yao

IPC: G09G3/32 ,  G09G3/3266 ,  G11C19/28

Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

公开(公告)号：US11328642B2

公开(公告)日：2022-05-10

申请号：US17044148

申请日：2020-03-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Lijun Yuan ,  Haoliang Zheng ,  Libin Liu ,  Xing Yao ,  Seungwoo Han

IPC: G09G3/20

Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.

公开(公告)号：US11244602B2

公开(公告)日：2022-02-08

申请号：US17086097

申请日：2020-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Dongni Liu ,  Minghua Xuan ,  Zhenyu Zhang ,  Li Xiao ,  Liang Chen ,  Hao Chen ,  Guangliang Shang ,  Lijun Yuan ,  Xing Yao

IPC: G09G3/32

Abstract: A shift register includes an input sub-circuit, a control sub-circuit, an output sub-circuit and a reset sub-circuit. The input sub-circuit is configured to transmit an input signal from an input signal terminal to a pull-up node. The control sub-circuit is configured to transmit a clock signal from a clock signal terminal to the control node. The output sub-circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a first output signal terminal, and to transmit a first voltage signal from a first voltage signal terminal to the first output signal terminal. The reset sub-circuit is configured to transmit the second voltage signal to the control node to reset the control node, and to transmit a third voltage signal from the third voltage signal terminal to the pull-up node to reset the pull-up node.

公开(公告)号：US11094277B2

公开(公告)日：2021-08-17

申请号：US16149432

申请日：2018-10-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang ,  Xing Yao ,  Lijun Yuan ,  Zhichong Wang ,  Mingfu Han ,  Yinglong Huang

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.

公开(公告)号：US10943552B2

公开(公告)日：2021-03-09

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik Im ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US10699627B2

公开(公告)日：2020-06-30

申请号：US16287403

申请日：2019-02-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yoonsung Um ,  Mingfu Han ,  Lijun Yuan ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/20

Abstract: A driving method of a display panel, a display panel and a display device are disclosed. The method includes: for a first row of sub-pixels and a second row, adjacent to the first row, of sub-pixels, during a display period of a first frame image, inputting data signals to the first row of sub-pixels in a first order, and inputting data signals to the second row of sub-pixels in a second order opposite to the first order; and during a display period of a second frame image adjacent to the first frame image, inputting data signals to the first row of sub-pixels in the second order and inputting data signals to the second row of sub-pixels in the first order.

公开(公告)号：US20200090611A1

公开(公告)日：2020-03-19

申请号：US15751066

申请日：2017-07-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Seung Woo Han ,  Jiha Kim ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang

IPC: G09G3/36

Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

公开(公告)号：US10540938B2

公开(公告)日：2020-01-21

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Jing Lv ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/20 ,  G11C19/18

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US10330975B2

公开(公告)日：2019-06-25

申请号：US15794298

申请日：2017-10-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhihe Jin ,  Seungwoo Han ,  Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Zhichong Wang ,  Lijun Yuan ,  Haoliang Zheng ,  Yunsik Im

IPC: G02F1/133 ,  G02F1/13357 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/19

Abstract: The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units.