-
公开(公告)号：US11328652B2
公开(公告)日：2022-05-10
申请号：US16650306
申请日：2019-03-28
Inventor： Peng Liu , Bailing Liu , Fuqiang Li , Zhichong Wang , Jing Feng , Xinglong Luan
IPC: G09G5/00 , G09G3/20 , G11C19/28 , G09G3/3266 , G09G3/36
Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
-
公开(公告)号：US11308838B2
公开(公告)日：2022-04-19
申请号：US17051738
申请日：2020-01-21
Inventor： Zhichong Wang , Fuqiang Li , Jing Feng , Peng Liu , Xinglong Luan
Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
-
公开(公告)号：US11176886B2
公开(公告)日：2021-11-16
申请号：US16319185
申请日：2018-05-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lijun Yuan , Mingfu Han , Zhichong Wang , Haoliang Zheng , Seungwoo Han , Guangliang Shang
IPC: G09G3/3258 , G09G3/3266 , G09G3/3275 , G09G3/3233 , G09G3/3208 , G09G3/3225
Abstract: The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality.
-
公开(公告)号：US20210209988A1
公开(公告)日：2021-07-08
申请号：US16769910
申请日：2020-01-08
Inventor： Zhichong Wang , Fuqiang Li , Peng Liu , Jing Feng , Xinglong Luan
Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes an input sub-circuit, a discharging control sub-circuit, a discharging sub-circuit, and an output sub-circuit. The input sub-circuit is configured to transmit an input signal at an input signal terminal to a first node under control of a voltage at a second node. The discharging control sub-circuit is configured to transmit a first clock signal at a first clock signal terminal to the second node under control of a voltage at the first node. The discharging sub-circuit is configured to transmit a first constant voltage signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node. The output sub-circuit is configured to transmit a second clock signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.
-
公开(公告)号：US20200258463A1
公开(公告)日：2020-08-13
申请号：US15768309
申请日：2017-10-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seungwoo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Zhichong Wang , Mingfu Han , Lijun Yuan , Yunsik IM , Jing Lv , Xue Dong
Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
-
Patent Agency Ranking
公开(公告)号：US10504469B2
公开(公告)日：2019-12-10
申请号：US15768948
申请日：2017-10-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC: G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
-
公开(公告)号：US10475409B2
公开(公告)日：2019-11-12
申请号：US15796463
申请日：2017-10-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Mingfu Han , Xing Yao , Guangliang Shang , Haoliang Zheng , Seung-Woo Han , Jiha Kim , Lijun Yuan , Zhichong Wang
Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.
-
公开(公告)号：US10269290B2
公开(公告)日：2019-04-23
申请号：US15680416
申请日：2017-08-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang Shang , Mingfu Han , Haoliang Zheng , Han-Seung- Woo , Im-Yun- Sik , Jing Lv , Yinglong Huang , Jun-Jung- Mok , Xue Dong , Zhichong Wang , Xing Yao , Lijun Yuan , Zhihe Jin
IPC: G09G3/36 , G09G3/20 , G11C19/28 , G09G3/3266
Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.
-
9.发明申请公开(公告)号：US20180190180A1
公开(公告)日：2018-07-05
申请号：US15680416
申请日：2017-08-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang Shang , Mingfu Han , Haoliang Zheng , Han-Seung- Woo , Im-Yun- Sik , Jing Lv , Yinglong Huang , Jun-Jung- Mok , Xue Dong , Zhichong Wang , Xing Yao , Lijun Yuan , Zhihe Jin
CPC classification number: G09G3/2092 , G09G3/3266 , G09G3/3677 , G09G2300/0809 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/043 , G09G2330/02 , G11C19/28
Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.
-
公开(公告)号：US12080226B2
公开(公告)日：2024-09-03
申请号：US18275012
申请日：2022-07-08
Inventor： Miao Liu , Xueguang Hao , Jingbo Xu , Xing Yao , Jingquan Wang , Xinyin Wu , Xinguo Li , Zhichong Wang
IPC: G09G3/3266 , G09G3/32 , G09G3/3208
CPC classification number: G09G3/32 , G09G3/3266 , G09G3/3208 , G09G2300/0408 , G09G2300/0426 , G09G2300/0809 , G09G2310/0267 , G09G2310/0286 , G09G2320/0223
Abstract: A display substrate, comprising a base substrate and a scan drive control circuit which is disposed in a non-display area of the base substrate. The scan drive control circuit comprises an input circuit, an output control circuit, and an output circuit. The output control circuit is connected to the input circuit and the output circuit. The output control circuit comprises a first node control capacitor and a second node control capacitor. The length of the first node control capacitor in a first direction LC1k, the length of the second node control capacitor in the first direction LC2k and the length of the scan drive control circuit in the first direction LY satisfy the following formula:
L
C
1
k
L
Y
-
-
-
-
-
-
-
-
-
Search Results
53
records
(took 0.026 seconds)
