公开(公告)号：US20110156039A1

公开(公告)日：2011-06-30

申请号：US12894665

申请日：2010-09-30

Applicant: Ju-Hyeon BAEK ,  Keum-Dong JUNG ,  Jong-Hwan LEE ,  Kyung-Wook KIM

Inventor： Ju-Hyeon BAEK ,  Keum-Dong JUNG ,  Jong-Hwan LEE ,  Kyung-Wook KIM

IPC: H01L33/08 ,  H01L21/28

CPC classification number: H01L21/68735 ,  G02F1/13394 ,  G02F2001/13396 ,  H01L21/563 ,  H01L21/6875 ,  H01L27/1214 ,  H01L27/1288 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display apparatus includes a display substrate and a counter substrate. The display substrate includes a first substrate and a plurality of pixel electrodes formed on the first substrate. The counter substrate includes a second substrate facing the first substrate, a common electrode formed on the second substrate, a first spacer formed on the common electrode and making contact with the display substrate, a second spacer having a first gap with the display substrate, a third spacer having a second gap larger than the first gap with the display substrate, and a fourth spacer having a third gap larger than the second gap with the display substrate.

Abstract translation: 显示装置包括显示基板和对置基板。 显示基板包括第一基板和形成在第一基板上的多个像素电极。 对置基板包括面向第一基板的第二基板，形成在第二基板上的公共电极，形成在公共电极上并与显示基板接触的第一间隔件，与显示基板具有第一间隙的第二间隔件， 第三间隔物，其具有比所述显示基板的所述第一间隙大的第二间隙，以及具有比所述显示基板的所述第二间隙大的第三间隙的第四间隔物。

公开(公告)号：US20100225870A1

公开(公告)日：2010-09-09

申请号：US12537348

申请日：2009-08-07

Applicant: Jae-Hyun PARK ,  Jong-Hwan LEE ,  Kyung-Wook KIM

Inventor： Jae-Hyun PARK ,  Jong-Hwan LEE ,  Kyung-Wook KIM

IPC: G02F1/1345 ,  G02F1/1333 ,  H01J9/00 ,  H01J9/50

CPC classification number: G02F1/136204 ,  G02F1/136259 ,  G02F2001/136263

Abstract: An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, data lines disposed in the display area and including a portion thereof extending from the display area into the peripheral area at a first side of a periphery of the display area, and a repair line disposed in the peripheral area and crossing the portion of the data lines extending into the peripheral area. The array substrate also includes a static electricity diode part electrically connected to the repair line and a first data line of the data lines.

Abstract translation: 阵列基板包括具有显示区域和围绕显示区域的外围区域的基板，设置在显示区域中的数据线，并且包括其在显示器的周边的第一侧处从显示区域延伸到周边区域的部分 以及设置在周边区域中并与延伸到周边区域的数据线的部分交叉的修复线。 阵列基板还包括电连接到修复线的静电二极管部分和数据线的第一数据线。

公开(公告)号：US20100158188A1

公开(公告)日：2010-06-24

申请号：US12575895

申请日：2009-10-08

Applicant: Hong-Woo LEE ,  Sung-Man KIM ,  Jong-Hyuk LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Sang-Moon MOH ,  Jeong-Il KIM ,  Yeon-Kyu MOON

Inventor： Hong-Woo LEE ,  Sung-Man KIM ,  Jong-Hyuk LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Sang-Moon MOH ,  Jeong-Il KIM ,  Yeon-Kyu MOON

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Abstract translation: 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

公开(公告)号：US20090294771A1

公开(公告)日：2009-12-03

申请号：US12183619

申请日：2008-07-31

Applicant: Beom-Jun KIM ,  Jong-Hwan LEE ,  Bum-Ki BAEK ,  Sung-Man KIM ,  Hye-Rhee HAN ,  Jong-Hyuk LEE ,  Yu-Jun KIM

Inventor： Beom-Jun KIM ,  Jong-Hwan LEE ,  Bum-Ki BAEK ,  Sung-Man KIM ,  Hye-Rhee HAN ,  Jong-Hyuk LEE ,  Yu-Jun KIM

IPC: H01L33/00

CPC classification number: G02F1/136204 ,  G02F1/1309 ,  G02F1/1345 ,  G02F2001/136254 ,  H01L22/32 ,  H01L27/0248 ,  H01L27/12 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate for a display panel includes a base substrate, a plurality of signal lines, a plurality of signal pads corresponding to first end portions of the signal lines, a shorting bar corresponding to second end portions of the signal lines, a plurality of bridge lines on the base substrate disposed between the signal line and the shorting bar which electrically connects the signal line and the shorting bar. A color filter array panel opposite a TFT LCD panel substrate includes a medium dam layer which fully overlaps the bridge lines of the TFT LCD panel substrate. A data TFT for inspection having a source electrode coupled to the signal line, a drain electrode coupled to any one of the shorting bars, and a gate electrode coupled to a data TFT driving signal line ensures the normal operation of the display panel after the array test.

Abstract translation: 用于显示面板的基板包括基底基板，多条信号线，对应于信号线的第一端部的多个信号焊盘，对应于信号线的第二端部的短路棒，多个桥接线 在设置在信号线和短路棒之间的基底基板上，该短路棒电连接信号线和短路棒。 与TFT LCD面板基板相对的滤色器阵列面板包括与TFT LCD面板基板的桥接线完全重叠的介质阻挡层。 用于检查的数据TFT具有耦合到信号线的源电极，耦合到任一个短路棒的漏电极和耦合到数据TFT驱动信号线的栅电极，确保阵列后的显示面板的正常操作 测试。

公开(公告)号：US20110116019A1

公开(公告)日：2011-05-19

申请号：US12899303

申请日：2010-10-06

Applicant: Jung-Hwan HWANG ,  Kyung-Wook KIM ,  Young-Joon CHO ,  Jong-Hwan LEE ,  Hye-Rhee HAN

Inventor： Jung-Hwan HWANG ,  Kyung-Wook KIM ,  Young-Joon CHO ,  Jong-Hwan LEE ,  Hye-Rhee HAN

IPC: G02F1/1333

CPC classification number: G02F1/13452 ,  G02F1/1341

Abstract: A liquid crystal display includes a first substrate and a second substrate facing each other, common voltage wiring disposed on the first substrate and transmitting a common voltage, a first insulating layer disposed on the common voltage wiring, a common electrode disposed on a whole surface of the second substrate, a first conductive member disposed between the first substrate and the second substrate and electrically connecting the common electrode and the common voltage wiring to each other, and a sealant combining the first substrate and the second substrate. The first insulating layer includes a first contact hole exposing a first portion of the common voltage wiring and a plurality of a second contact hole exposing a second portion of the common voltage wiring, the second contact hole having a smaller area than the first contact hole.

Abstract translation: 液晶显示器包括：第一基板和第二基板;第一基板和第二基板;公共电压布线，布置在第一基板上并传输公共电压;第一绝缘层，设置在公共电压布线上;公共电极，设置在整个表面上 所述第二基板，设置在所述第一基板和所述第二基板之间并将所述公共电极和所述公共电压布线彼此电连接的第一导电构件，以及组合所述第一基板和所述第二基板的密封剂。 第一绝缘层包括暴露公共电压布线的第一部分的第一接触孔和暴露公共电压布线的第二部分的多个第二接触孔，第二接触孔具有比第一接触孔小的面积。

公开(公告)号：US20080001904A1

公开(公告)日：2008-01-03

申请号：US11761149

申请日：2007-06-11

Applicant: Sung-Man KIM ,  Myung-Koo HUR ,  Jong-Hwan LEE ,  Hong-Woo LEE

Inventor： Sung-Man KIM ,  Myung-Koo HUR ,  Jong-Hwan LEE ,  Hong-Woo LEE

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G11C19/28

Abstract: A gate driving circuit includes stages connected in series. In a stage, a pull-up part pulls up a present gate signal to a level of a first clock signal, and a pull-down part receives a next gate signal from a next stage to discharge the present gate signal to an off-voltage. A pull-up driving part turns on or turns off the pull-up part and the carry part. A holding part holds the present gate signal at the off-voltage and a present inverter turns on or turns off the holding part in response to the first clock signal. A ripple preventing capacitor is connected between a present node and an output terminal of a previous stage's inverter to prevent a ripple at the present Q-node in response to an output signal from the previous inverter.

Abstract translation: 栅极驱动电路包括串联连接的级。 在一个阶段中，上拉部分将当前栅极信号提升到第一时钟信号的电平，并且下拉部分从下一级接收下一个栅极信号，以将当前栅极信号放电到截止电压 。 上拉驱动部分打开或关闭上拉部分和进位部分。 保持部分将当前门信号保持在截止电压，并且本逆变器响应于第一时钟信号而导通或关断保持部分。 防波电容器连接在前级逆变器的当前节点和输出端之间，以防止来自前一个逆变器的输出信号在当前Q节点处产生纹波。