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公开(公告)号：US06588008B1
公开(公告)日：2003-07-01
申请号：US09546755
申请日：2000-04-11
IPC分类号： G06F945
CPC分类号： G06F9/30043 , G06F8/47 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/3885
摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.
摘要翻译： 一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。 重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。 本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。 汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。 本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。
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12.发明授权Network processor which makes thread execution control decisions based on latency event lengths 失效基于延迟事件长度的线程执行控制决策的网络处理器公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译： 在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。 排队多个独立的指令执行线程使其能够快速访问共享存储器。 如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。 当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。 当短暂延迟事件完成时，控制返回到原始线程。 每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。 线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。
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公开(公告)号：US07089555B2
公开(公告)日：2006-08-08
申请号：US10179100
申请日：2002-06-25
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
CPC分类号： G06F9/526
摘要： An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.
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公开(公告)号：US06931641B1
公开(公告)日：2005-08-16
申请号：US09542206
申请日：2000-04-04
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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15.发明授权公开(公告)号：US06785278B1
公开(公告)日：2004-08-31
申请号：US09210222
申请日：1998-12-10
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
IPC分类号： H04L1228
CPC分类号： H04L12/4625 , H04L45/745
摘要： Methods systems and computer program products are provided for hashing address values that exhibit banding in a plurality of regions of an address space defined by at least two segments of the address values, by performing at least one of a translation and a rotation of the at least two segments to thereby map the at least two segments from the plurality of regions to one of the plurality of regions.
摘要翻译： 提供了方法系统和计算机程序产品，用于通过执行至少一个地址值的平移和旋转中的至少一个来散列地址值，所述地址值在由地址值的至少两个段定义的地址空间的多个区域中呈现带状 从而将多个区域中的至少两个区段映射到多个区域中的一个区域。
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公开(公告)号：US07917908B2
公开(公告)日：2011-03-29
申请号：US12137818
申请日：2008-06-12
申请人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr. , Wesley Erich Queen , Michael Steven Siegel
发明人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr. , Wesley Erich Queen , Michael Steven Siegel
CPC分类号： G06F9/52
摘要： In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
摘要翻译： 在有序信号量管理系统中，待处理状态允许线程不竞争锁定的信号量绕过一个或多个线程等待相同的锁定信号量。 挂起级别的数量决定了可绕过同一锁定信号量的连续线程的数量。 当提供多个级别时，挂起的级别按排队顺序排列优先级。
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17.发明授权公开(公告)号：US07454753B2
公开(公告)日：2008-11-18
申请号：US10179860
申请日：2002-06-25
申请人： Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
发明人： Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
CPC分类号： G06F9/52
摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.
摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。
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公开(公告)号：US07406690B2
公开(公告)日：2008-07-29
申请号：US10247602
申请日：2002-09-19
申请人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr. , Wesley Erich Queen , Michael Steven Siegel
发明人： Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr. , Wesley Erich Queen , Michael Steven Siegel
CPC分类号： G06F9/52
摘要： In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
摘要翻译： 在有序信号量管理系统中，待处理状态允许线程不竞争锁定的信号量绕过一个或多个线程等待相同的锁定信号量。 挂起级别的数量决定了可绕过同一锁定信号量的连续线程的数量。 当提供多个级别时，挂起的级别按排队顺序排列优先级。
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公开(公告)号：US07143414B2
公开(公告)日：2006-11-28
申请号：US10247673
申请日：2002-09-19
CPC分类号： G06F9/52
摘要： Processor threads in a multi-processor system can concurrently lock multiple semaphores by providing a lock command which includes the semaphore value and a semaphore number. Each processor is allocated two or more addressable semaphore stores, each of which include a multi-bit field identifying the requested semaphore and a one bit field identifying the locked status of the requested semaphore. The semaphore number determines which of the allocated semaphore stores are to be used for processing the lock command.
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