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公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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2.发明授权Network processor which makes thread execution control decisions based on latency event lengths 失效基于延迟事件长度的线程执行控制决策的网络处理器公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译： 在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。 排队多个独立的指令执行线程使其能够快速访问共享存储器。 如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。 当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。 当短暂延迟事件完成时，控制返回到原始线程。 每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。 线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。
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公开(公告)号：US06931641B1
公开(公告)日：2005-08-16
申请号：US09542206
申请日：2000-04-04
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译： 机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。
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公开(公告)号：US07440417B2
公开(公告)日：2008-10-21
申请号：US10870730
申请日：2004-06-17
申请人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
发明人： Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel , Jean Louis Calvignac , Gordon Taylor Davis
IPC分类号： H04L12/28
摘要： A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.
摘要翻译： 公开了一种用于数据处理的系统中的协议和帧分类的系统和方法，包括：根据预定的测试分析一部分数据包或帧，以及存储该数据包的特性以用于帧的后续处理。 这些特征优选地通过硬件获得，硬件在快速且均匀的时间周期内这样做。 然后，分组的存储特性由网络处理复合体用于帧的进一步处理。 处理器使用开始指令地址或者入门点进行预处理，并且第3层头的开始位置以及帧类型的标志。
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公开(公告)号：US06775284B1
公开(公告)日：2004-08-10
申请号：US09479027
申请日：2000-01-07
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Michael Steven Siegel
IPC分类号： H04L1256
摘要： A system and method of protocol and frame classification in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the packet or frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit, such as the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address and flags indicating whether the frame uses a virtual local area network, preferably using hardware to quickly and in a uniform time period. The stored key characteristics of the packet are then used by the network processing complexes in its further processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additionally, additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions.
摘要翻译： 用于数据处理（例如，切换或路由数据分组或帧）的系统中的协议和帧分类的系统和方法。 本发明包括根据预定的测试来分析分组或帧的一部分，然后存储该分组的关键特征以用于该帧的后续处理。 帧（或输入信息单元，例如帧中使用的层3协议的类型，第2层封装技术，起始指令地址和指示帧是否使用虚拟局域网的标志）的关键特性，优选地使用 硬件在快速和统一的时间段内，存储的密钥特性随后由网络处理复合体在帧的进一步处理中被使用，处理器使用起始指令地址和开始指令的位置进行预处理 第3层标题以及帧类型的标志，即处理器使用指令地址或代码入口点，根据帧类型对正确位置的帧开始处理，另外附加指令 地址可以在分支上顺序堆叠和使用，以避免额外的测试和分支指令。
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公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译： 嵌入式处理器复合体包含多个协议处理器单元（PPU）。 每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。 每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。 操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。 指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。
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公开(公告)号：US07089555B2
公开(公告)日：2006-08-08
申请号：US10179100
申请日：2002-06-25
申请人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
发明人： Jean Louis Calvignac , Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
CPC分类号： G06F9/526
摘要： An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.
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8.发明授权公开(公告)号：US07454753B2
公开(公告)日：2008-11-18
申请号：US10179860
申请日：2002-06-25
申请人： Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
发明人： Gordon Taylor Davis , Marco Heddes , Steven Kenneth Jenkins , Ross Boyd Leavens , Robert Brian Likovich, Jr.
CPC分类号： G06F9/52
摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.
摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。
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公开(公告)号：US07409520B2
公开(公告)日：2008-08-05
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。
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公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。
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