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    Semaphore management subsystem for use with multi-thread processor systems
    2.
    发明授权
    Semaphore management subsystem for use with multi-thread processor systems 失效
    用于多线程处理器系统的信号量管理子系统

    公开(公告)号：US07454753B2

    公开(公告)日：2008-11-18

    申请号：US10179860

    申请日：2002-06-25

    申请人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    发明人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/52

    摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

    摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。

    Network processor with single interface supporting tree search engine and CAM
    4.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07953077B2

    公开(公告)日：2011-05-31

    申请号：US11457952

    申请日：2006-07-17

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    Network processor with single interface supporting tree search engine and CAM
    5.
    发明授权
    Network processor with single interface supporting tree search engine and CAM 失效
    具有单界面支持树搜索引擎和CAM的网络处理器

    公开(公告)号：US07167471B2

    公开(公告)日：2007-01-23

    申请号：US09940758

    申请日：2001-08-28

    申请人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    发明人： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

    摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

    摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

    Chip to chip interface for interconnecting chips
    6.
    发明授权
    Chip to chip interface for interconnecting chips 失效
    用于互连芯片的芯片到芯片接口

    公开(公告)号：US06910092B2

    公开(公告)日：2005-06-21

    申请号：US10016800

    申请日：2001-12-10

    申请人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Louis Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/42

    CPC分类号： G06F13/4265

    摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

    摘要翻译： 网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。 可选的调度器芯片耦合到数据流芯片。 命名的组件被复制以创建对称的入口和出口结构。 芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

    Eliminating memory corruption when performing tree functions on multiple threads
    9.
    发明授权
    Eliminating memory corruption when performing tree functions on multiple threads 有权
    在多个线程上执行树函数时，消除内存损坏

    公开(公告)号：US07036125B2

    公开(公告)日：2006-04-25

    申请号：US10217529

    申请日：2002-08-13

    申请人： Claude Basso ,  Matthew William Kilpatrick Brown ,  Gordon Taylor Davis ,  Marco Heddes ,  Piyush Chunilal Patel ,  Grayson Warren Randall ,  Sonia Kiang Rovner ,  Colin Beaton Verrilli

    发明人： Claude Basso ,  Matthew William Kilpatrick Brown ,  Gordon Taylor Davis ,  Marco Heddes ,  Piyush Chunilal Patel ,  Grayson Warren Randall ,  Sonia Kiang Rovner ,  Colin Beaton Verrilli

    IPC分类号： G06F9/46 ,  G06F12/00

    CPC分类号： G06F9/52

    摘要： A method, system and computer program product for eliminating memory corruption when performing multi-threaded tree operations. A network processor may receive a command to perform a tree operation on a tree on one or more of multiple threads. Upon performing the requested tree operation, the network processor may lock one or more resources during a portion of the execution of the requested tree operation using one or more semaphores. A semaphore may refer to a flag used to indicate whether to “lock” or make available the resource associated with the semaphore. Locking may refer to preventing the resource from being available to other threads. Hence, by locking one or more resources during a portion of the tree operation, memory corruption may be eliminated in a multiple thread system while preventing these resources from being used by other threads for a minimal amount of time.

    摘要翻译： 一种用于在执行多线程树操作时消除内存损坏的方法，系统和计算机程序产品。 网络处理器可以在多个线程中的一个或多个上接收在树上执行树操作的命令。 在执行所请求的树操作时，网络处理器可以在使用一个或多个信号量的所请求的树操作的执行的一部分期间锁定一个或多个资源。 信号量可以指用于指示是否“锁定”或提供与信号量相关联的资源的标志。 锁定可能是指防止资源对其他线程可用。 因此，通过在树操作的一部分期间锁定一个或多个资源，可以在多线程系统中消除内存损坏，同时防止这些资源在最短时间内被其他线程使用。

    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory
    10.
    发明申请
    System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory 审中-公开
    具有由具有分布式片上共享存储器和外部共享存储器的片上网络链接的可编程处理元件阵列的片上系统

    公开(公告)号：US20100191911A1

    公开(公告)日：2010-07-29

    申请号：US12639325

    申请日：2009-12-16

    申请人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    发明人： Marco Heddes ,  Massimo Ravasi ,  Rakesh Kumar Malik ,  Timothy M. Shanley ,  Michael Singngee Yeo

    IPC分类号： G06F15/80 ,  G06F9/06 ,  G06F12/08 ,  G06F12/02

    CPC分类号： G06F15/16

    摘要： An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

    摘要翻译： 具有可编程处理元件阵列的集成电路和由片上通信网络链接的存储器接口。 每个处理元件包括多个处理核心和本地存储器。 存储器接口块可操作地耦合到外部存储器和片上通信网络。 存储器接口支持通过片上通信网络响应于从阵列的处理元件传送的消息来访问外部存储器。 阵列的多个处理元件的一部分本地存储器的一部分以及外部存储器的一部分都被分配以在执行分配在其上的编程操作期间存储由阵列的多个处理元件共享的数据。