公开(公告)号：US09065464B2

公开(公告)日：2015-06-23

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。