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    DYNAMIC POWER PROFILING
    12.
    发明申请
    DYNAMIC POWER PROFILING 有权
    动态电源轮廓

    公开(公告)号：US20140218011A1

    公开(公告)日：2014-08-07

    申请号：US13950750

    申请日：2013-07-25

    Applicant: Broadcom Corporation

    Inventor： Walid Nabhane ,  Mark D. Rutherford ,  Chun-Nan Ke ,  Veronica Alarcon ,  John Russell Platenak ,  Arun Palaniappan

    IPC: G01R19/00

    CPC classification number: G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    Abstract: Aspects of dynamic power profiling are described herein. In various embodiments, a current sense operating mode is set for a current sense circuit, and the current sense circuit is enabled for operation. The current sense circuit senses an amount of current supplied by at least one of a plurality of power rails based on the current sense operating mode. The current sense circuit also accumulates and stores a value of the amount of current over a period of time. In certain aspects, a system controller averages the value of the amount of current based on the period of time. The current sense circuit may be configured to operate in various modes of operation including single or scan rail modes of operation, and the average of the value of the amount of current may be evaluated based on the modes of operation of the current sense circuit and/or the system.

    Abstract translation: 这里描述了动态功率分析的方面。 在各种实施例中，为电流感测电路设置电流感测操作模式，并且使电流感测电路能够进行操作。 电流感测电路基于电流感测操作模式感测由多个电源轨道中的至少一个提供的电流量。 电流检测电路还累积并存储一段时间内的电流量的值。 在某些方面，系统控制器基于该时间段对电流量的值进行平均。 电流检测电路可以被配置为在包括单轨或扫描轨操作模式的各种操作模式下操作，并且可以基于电流检测电路的操作模式和/或电流检测电路的操作模式来评估电流量的平均值， 或系统。

    SATELLITE CHANNEL AND LTE COEXISTENCE
    13.
    发明申请
    SATELLITE CHANNEL AND LTE COEXISTENCE 有权

    公开(公告)号：US20170245189A1

    公开(公告)日：2017-08-24

    申请号：US15076156

    申请日：2016-03-21

    Applicant: BROADCOM CORPORATION

    Inventor： Walid Nabhane ,  Xiaoxin Qiu ,  Jason C. Demas ,  Pascal G. Finkenbeiner

    IPC: H04W36/20 ,  H04W36/28 ,  H04W72/04

    CPC classification number: H04W36/20 ,  H04W16/14 ,  H04W36/28 ,  H04W72/0453

    Abstract: Systems and methods of handling satellite channel and LTE coexistence are provided. A first device can identify at least one first frequency band. The first device can determine that at least one second frequency band of a plurality of second frequency bands overlaps with the at least one first frequency band. In response to determining that the at least one second frequency band overlaps with the at least one first frequency band, the first device transmits a message including an identifier of the first device and an indication of the at least one second frequency band to a second device. The second device receives the message. The second device, in response to receiving a channel request from the first device, allocates, from the plurality of second frequency bands, a second frequency band different from the at least one second frequency band.

    CHARGER DETECTION AND OPTIMIZATION PRIOR TO HOST CONTROL
    15.
    发明申请
    CHARGER DETECTION AND OPTIMIZATION PRIOR TO HOST CONTROL 有权
    在主机控制之前的充电器检测和优化

    公开(公告)号：US20140223200A1

    公开(公告)日：2014-08-07

    申请号：US13950762

    申请日：2013-07-25

    Applicant: Broadcom Corporation

    Inventor： Walid Nabhane ,  Mark D. Rutherford ,  Narayan Prasad Ramachandran ,  David Chang ,  Yi Ting Chen ,  Chenmin Zhang ,  Ajmal A. Godil

    IPC: G06F1/26 ,  G01R31/36 ,  H02J7/00

    CPC classification number: G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.

    Abstract translation: 这里描述了在主机控制之前的充电器检测和优化的方面。 在各种实施例中，检测到在系统总线上是否存在反向电流的状况。 当存在反向电流的条件时，反向电流被各种反向电流吸收电路中的一个或多个吸收。 通过依靠一个或多个反向电流宿电路，为了安全起见，寻址或减轻反向电流的条件，检测器可能能够识别或区分耦合到系统总线的几种不同类型的充电器或充电端口，允许 要充分选择充电器。 此外，耦合到系统总线的充电器或充电端口的类型的指示器通过单个引脚接口传送，以便与仅能够识别两种不同类型的充电器之间的电路向后兼容。

    POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT
    16.
    发明申请
    POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT 有权
    电源模式注册减少和功率轨道增强

    公开(公告)号：US20140223153A1

    公开(公告)日：2014-08-07

    申请号：US13950738

    申请日：2013-07-25

    Applicant: Broadcom Corporation

    Inventor： Chih-Tsung Hsieh ,  Hao-zheng Lee ,  Walid Nabhane ,  Veronica Alarcon ,  Mark Norman Fullerton

    IPC: G06F1/26

    CPC classification number: G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    Abstract: Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.

    Abstract translation: 描述了功率模式寄存器减少和电源轨的改进方案。 在一个实施例中，用于第一电力轨的操作参数由功率管理电路根据预定的编程设置来设置。 关于等待时间，电源轨已启用，并且处理器被释放以启动。 反过来，通过高速接口从处理器接收修改第一电力轨的操作参数的命令或用于设置第二电力轨的操作参数的命令中的至少一个。 通过访问一组电源轨的分组操作寄存器，处理器可以一次更新或修改整组电源轨的设置。 结合处理器，电源管理电路可以以灵活和有效的方式加电多个电源轨。

    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES
    17.
    发明申请
    CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES 有权
    时钟交叉串行接口，直接锁定和响应代码

    公开(公告)号：US20140223031A1

    公开(公告)日：2014-08-07

    申请号：US13950713

    申请日：2013-07-25

    Applicant: Broadcom Corporation

    Inventor： Veronica Alarcon ,  Walid Nabhane ,  Mark Norman Fullerton ,  Love Kothari ,  Ronak Subhas Patel ,  Chih-Tsung Hsieh ,  Hao-zheng Lee

    IPC: G06F13/12

    CPC classification number: G06F11/1048 ,  G01R19/003 ,  G01R31/36 ,  G01R31/40 ,  G05F1/625 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/1016 ,  G06F11/3031 ,  G06F11/3058 ,  G06F11/3062 ,  G06F11/3093 ,  G06F13/126 ,  G11C7/106 ,  G11C7/1072 ,  H02J7/0029 ,  Y02D10/171

    Abstract: Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

    Abstract translation: 描述串行接口的时钟域，串行接口上​​的直接锁存和响应代码的方面。 在各种实施例中，识别通过串行接口接收的数据通信命令，并且解析通过串行接口接收的地址以访问寄存器组。 在写操作中，根据地址是否落在寄存器组的直接锁存地址范围内，数据可以被直接锁存到寄存器组的直接锁存寄存器中或者先进先出寄存器。 对于读和写操作，可以参考串行接口的状态寄存器来识别或减轻错误状况，并且可以依赖等待时间来考虑时钟域穿越。 在每次读取和写入操作之后，可以传送包括状态指示器的响应代码。

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