公开(公告)号：US08880983B2

公开(公告)日：2014-11-04

申请号：US14063778

申请日：2013-10-25

Applicant: Broadcom Corporation

Inventor： Zhongfeng Wang ,  Chung-Jue Chen ,  Kang Xiao ,  Hongtao Jiang ,  James R. Fife ,  Sudeep Bhoja

IPC: H03M13/00 ,  H04L1/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  H04L1/005 ,  H04L1/0064

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such (e.g., possibly by performing bit-flipping), various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Abstract translation: 采用其中选择性附加循环冗余校验（CRC）的二进制产品编码的通信设备。 产品代码编码（例如，采用矩阵格式化的比特的行和列编码，选择性地具有其中的比特的交织和/或置换）可以与附加的纠错码（ECC）或前向纠错（FEC）编码相结合，从而产生编码 用于产生要发送到通信信道中的信号的位可以采用各种ECC / FEC，包括BCH（Bose和Ray-Chaudhuri和Hocquenghem）码，Reed-Solomon（RS）码，LDPC（低密度 奇偶校验）码等。使用本文原理生成的编码信号的冗余在大约7％的范围内，并且可以对这里生成的这种编码信号进行硬判决解码。 根据这样的解码（例如，可能通过执行比特翻转），可以有选择地忽略各种比特决定（在某些迭代内）和/或返回到先前的比特决定。

公开(公告)号：US20130208771A1

公开(公告)日：2013-08-15

申请号：US13751407

申请日：2013-01-28

Applicant: BROADCOM CORPORATION

Inventor： Zhongfeng Wang

IPC: H04L25/02

CPC classification number: H04L25/02 ,  H04L1/0057 ,  H04L25/4904 ,  H04L25/4908

Abstract: Disclosed herein are certain embodiments of a coding system and method that guarantee a pair of sync bits in a transcoded block will appear on the same physical lane. Embodiments may then use this property for data synchronization and to guarantee a bit transition in a certain amount of time on a physical lane. Embodiments of a coding system and process for configuring alignment marker blocks are also disclosed.

Abstract translation: 这里公开了保证代码转换块中的一对同步位将出现在同一物理通道上的编码系统和方法的某些实施例。 然后，实施例可以使用该属性进行数据同步，并保证在物理通道上一定时间内的位转换。 还公开了用于配置对准标记块的编码系统和过程的实施例。

公开(公告)号：US09231622B2

公开(公告)日：2016-01-05

申请号：US13930909

申请日：2013-06-28

Applicant: Broadcom Corporation

Inventor： Zhongfeng Wang

IPC: G06F11/00 ,  H03M13/00 ,  H03M13/29 ,  H03M13/15

CPC classification number: H03M13/2909 ,  H03M13/152 ,  H03M13/1595 ,  H03M13/2903 ,  H03M13/6575

Abstract: A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits.

Abstract translation: 提供了数据编码电路和相应的方法。 数据编码电路包括与编码器部分通信的第一数据格式化器。 第一数据格式化器被配置为以串行方式接收源数据块并输出并行二维源数据。 编码器接收并行二维源数据，并且从平行二维源数据计算出纠错码的多个串行行奇偶校验位和多个并行列奇偶校验位。 第二数据格式化器与编码器部分通信并接收并行列奇偶校验位并输出串行列奇偶校验位。